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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250062282A1

    公开(公告)日：2025-02-20

    申请号：US18892978

    申请日：2024-09-23

    Applicant: DENSO CORPORATION

    Inventor： SHINGO TSUCHIMOCHI

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L27/07

    Abstract: A semiconductor device includes a first insulating substrate and a first semiconductor element joined to the first insulating substrate through the first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer disposed at a side of the first insulating layer. The first inner conductive layer includes a surface having a first region and a second region. The second region surrounds the first region and has larger surface roughness than the first region. The first conductive spacer is joined to the first region of the first inner conductive layer through a first junction layer.

    Semiconductor device and method for designing thereof
    3.
    发明授权
    Semiconductor device and method for designing thereof 有权

    公开(公告)号：US12211903B2

    公开(公告)日：2025-01-28

    申请号：US17829168

    申请日：2022-05-31

    Applicant: mqSemi AG

    Inventor： Munaf Rahimo ,  Iulian Nistor

    IPC: H01L29/10 ,  H01L27/07 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

    Abstract: A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

    SEMICONDUCTOR DEVICE CONFIGURED FOR GATE DIELECTRIC MONITORING
    4.
    发明申请
    SEMICONDUCTOR DEVICE CONFIGURED FOR GATE DIELECTRIC MONITORING 有权

    公开(公告)号：US20250004034A1

    公开(公告)日：2025-01-02

    申请号：US18734307

    申请日：2024-06-05

    Applicant: Analog Devices International Unlimited Company

    Inventor： Edward John Coyne ,  John P. Meskell ,  Colm Patrick Heffernan ,  Mark Forde ,  Shane Geary

    IPC: G01R31/26 ,  H01L27/07 ,  H01L29/10 ,  H01L29/735 ,  H01L29/78

    Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

    Diode structures of stacked devices and methods of forming the same
    6.
    发明授权
    Diode structures of stacked devices and methods of forming the same 有权

    公开(公告)号：US12094869B2

    公开(公告)日：2024-09-17

    申请号：US18366010

    申请日：2023-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

    IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/07 ,  H01L29/739 ,  H01L29/861

    CPC classification number: H01L27/0255 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0727 ,  H01L29/7391 ,  H01L29/861

    Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

    Reverse conducting insulated gate power semiconductor device having low conduction losses
    7.
    发明授权
    Reverse conducting insulated gate power semiconductor device having low conduction losses 有权

    公开(公告)号：US12068312B2

    公开(公告)日：2024-08-20

    申请号：US17442019

    申请日：2020-03-13

    Applicant: Hitachi Energy Ltd

    Inventor： Charalampos Papadopoulos ,  Munaf Rahimo ,  Chiara Corvasce

    IPC: H01L27/00 ,  H01L27/07 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L29/78

    CPC classification number: H01L27/0727 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/7805 ,  H01L29/8613

    Abstract: A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells (40) and a pilot diode unit cell (50) comprising a second conductivity type anode region (51) in direct contact with a first main electrode (21) and extending from a first main side (11) to a first depth (d1). Each active unit cell (40) comprises a first conductivity type first source layer (41a) in direct contact with the first main electrode (21), a second conductivity type base layer (42) and a first gate electrode (47a), which is separated from the first source layer (41a) and the second conductivity type base layer (42) by a first gate insulating layer (46a) to form a first field effect transistor structure. A lateral size (w) of the anode region (51) in an orthogonal projection onto a vertical plane perpendicular to the first main side (11) is equal to or less than 1 μm. On a first lateral side surface of the anode region (51) a first insulating layer (52a) is arranged and on an opposing second lateral side surface of the anode region (51) a second insulating layer (52b) is arranged. And a distance between the first insulating layer (52a) and the second insulating layer (52b) is equal to or less than 1 μm, the first insulating layer (52a) extending vertically from the first main side (11) to a second depth (d2), and the second insulating layer (52b) extending vertically from the first main side (11) to a third depth (d3), wherein the first depth (d1) is less than the second depth (d2) and less than the third depth (d3).

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240234554A1

    公开(公告)日：2024-07-11

    申请号：US18515275

    申请日：2023-11-21

    Applicant: FUJI ELECTRIC CO., LTD.

    Inventor： Naoki MITAMURA

    IPC: H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861

    CPC classification number: H01L29/7397 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/861

    Abstract: Provided is a semiconductor device including a transistor portion and a diode portion, where the semiconductor device including: a plurality of trench portions provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode portion; a low concentration region provided above the anode region and having a doping concentration an absolute value of which is lower than that of the anode region; and a high concentration region of the second conductivity type provided above the anode region and having a doping concentration higher than that of the anode region.

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