公开(公告)号：US11282845B2

公开(公告)日：2022-03-22

申请号：US15685690

申请日：2017-08-24

申请人： Micron Technology, Inc.

发明人： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC分类号： H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

摘要： A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20210193810A1

公开(公告)日：2021-06-24

申请号：US16837961

申请日：2020-04-01

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Pengkai Xu ,  Fulong Qiao ,  Yi Wang

IPC分类号： H01L29/423 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11539 ,  H01L27/11541 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28

摘要： A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

公开(公告)号：US10720439B2

公开(公告)日：2020-07-21

申请号：US15404005

申请日：2017-01-11

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： Changgeng Song

IPC分类号： H01L27/11573 ,  H01L27/11543 ,  H01L21/28 ,  H01L21/764 ,  H01L27/11539 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11524 ,  H01L27/11541 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/06 ,  H01L29/49 ,  H01L27/1157

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.

公开(公告)号：US20200168740A1

公开(公告)日：2020-05-28

申请号：US16775507

申请日：2020-01-29

申请人： David Liu

发明人： David Liu

IPC分类号： H01L29/788 ,  H01L29/78 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/10 ,  H01L27/11541 ,  H01L27/11558 ,  H01L29/423

摘要： An integrated circuit includes two different types of embedded memories, with cells that have different retention characteristics, and situated in different areas of the substrate. In some applications the cells are both non-volatile memories sharing a common gate layer but with different oxide layers, different thicknesses, etc. The first type of cell is a conventional flash cell which can be part of a logic/memory region, while the second type of cell uses capacitive coupling and can be located in a high voltage region. Because of their common features, the need for additional masks, manufacturing steps, etc. can be mitigated.

公开(公告)号：US20190355734A1

公开(公告)日：2019-11-21

申请号：US16529608

申请日：2019-08-01

申请人： SK hynix Inc.

发明人： Kang Sik CHOI

IPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11541

摘要： A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.

公开(公告)号：US10418372B2

公开(公告)日：2019-09-17

申请号：US15850225

申请日：2017-12-21

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/11556 ,  H01L27/11541 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.

公开(公告)号：US10224108B2

公开(公告)日：2019-03-05

申请号：US15860786

申请日：2018-01-03

申请人： eMemory Technology Inc.

发明人： Wen-Hao Ching ,  Shih-Chen Wang

IPC分类号： G11C16/14 ,  H03K19/088 ,  H01L27/11541 ,  G11C7/04 ,  G11C7/10 ,  G11C16/12 ,  G11C16/04 ,  H01L27/11558 ,  H01L29/423 ,  G11C16/26 ,  H01L27/11524 ,  G11C16/34 ,  H01L29/78 ,  H03K17/082 ,  H01L29/788

摘要： A non-volatile memory includes a first memory cell. The first memory cell includes five transistors and a first capacitor. The first transistor includes a first gate, a first terminal and a second terminal. The second transistor includes a second gate, a third terminal and a fourth terminal. The third transistor includes a third gate, a fifth terminal and a sixth terminal. The fourth transistor includes a fourth gate, a seventh terminal and an eighth terminal. The fifth transistor includes a fifth gate, a ninth terminal and a tenth terminal. The first capacitor is connected between the third gate and a control line. The third gate is a floating gate. The second terminal is connected with the third terminal. The fourth terminal is connected with the fifth terminal. The sixth terminal is connected with the seventh terminal. The eighth terminal is connected with the ninth terminal.

公开(公告)号：US20180269218A1

公开(公告)日：2018-09-20

申请号：US15704667

申请日：2017-09-14

申请人： Toshiba Memory Corporation

发明人： Tatsuya KATO ,  Fumitaka Arai ,  Kohei Sakaike ,  Satoshi Nagashima

IPC分类号： H01L27/11524 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/1156 ,  H01L27/11541

CPC分类号： H01L27/11524 ,  H01L27/11541 ,  H01L27/11556 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573

摘要： A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.

公开(公告)号：US09882566B1

公开(公告)日：2018-01-30

申请号：US15631384

申请日：2017-06-23

申请人： eMemory Technology Inc.

发明人： Chen-Hao Po ,  Wu-Chang Chang

IPC分类号： H03K19/094 ,  H03K19/088 ,  H01L27/11541 ,  H03K17/082

CPC分类号： G11C16/14 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/109 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3472 ,  H01L27/11524 ,  H01L27/11541 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/42364 ,  H01L29/7841 ,  H01L29/7883 ,  H03K17/0828 ,  H03K19/088

摘要： A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives an input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal.

公开(公告)号：US11374103B2

公开(公告)日：2022-06-28

申请号：US16837961

申请日：2020-04-01

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Pengkai Xu ,  Fulong Qiao ,  Yi Wang

IPC分类号： H01L29/423 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11539 ,  H01L27/11541 ,  H01L29/66 ,  H01L29/788

摘要： A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.