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    Reducing parasitic capacitance in a qubit system
    2.
    发明授权
    Reducing parasitic capacitance in a qubit system 有权

    公开(公告)号：US11672188B2

    公开(公告)日：2023-06-06

    申请号：US16977673

    申请日：2018-03-26

    申请人： Google LLC

    发明人： Rami Barends

    IPC分类号： G06N10/00 ,  H01L27/18 ,  H01L39/12 ,  H01L39/22 ,  H01P3/00

    CPC分类号： H01L27/18 ,  G06N10/00 ,  H01L39/125 ,  H01L39/223 ,  H01P3/003

    摘要： A system that includes: an array of qubits, each qubit of the array of qubits comprising a first electrode corresponding to a first node and a second electrode corresponding to a second node, wherein, for a first qubit in the array of qubits, the first qubit is positioned relative to a second qubit in the array of qubits such that a charge present on the first qubit induces a same charge on each of the first node of the second qubit and the second node of the second qubit, such that coupling between the first qubit and the second qubit is reduced, and wherein none of the nodes share a common ground is disclosed.

    SUPERCONDUCTING QUANTUM CIRCUIT
    3.
    发明公开
    SUPERCONDUCTING QUANTUM CIRCUIT 审中-公开

    公开(公告)号：US20230142878A1

    公开(公告)日：2023-05-11

    申请号：US17978356

    申请日：2022-11-01

    申请人： NEC Corporation

    发明人： Tomohiro YAMAJI

    IPC分类号： G01R33/035 ,  G06N10/40 ,  H01L39/22 ,  H01L27/18 ,  H01L39/02

    CPC分类号： G01R33/0354 ,  G06N10/40 ,  H01L39/223 ,  H01L27/18 ,  H01L39/025

    摘要： A superconducting quantum circuit includes a plurality of SQUIDs (Superconducting Quantum Interference Devices) connected in parallel, each of the plurality of SQUIDs including a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction connected in a loop, wherein a junction area of the first Josephson junction and a junction area of the second Josephson junction are different from each other, the plurality of SQUIDs configured to be mutually different in either one or both of: a sum of the junction area of the first Josephson junction and the junction area of the second Josephson junction; and a ratio of the junction area of the first Josephson junction to the junction area of the second Josephson junction.

    Hybrid photonics-solid state quantum computer
    4.
    发明授权
    Hybrid photonics-solid state quantum computer 有权

    公开(公告)号：US11625060B2

    公开(公告)日：2023-04-11

    申请号：US17706791

    申请日：2022-03-29

    申请人： ANYON SYSTEMS INC.

    发明人： Alireza Najafi-Yazdi

    IPC分类号： H04B10/70 ,  G06E3/00 ,  G06N10/00 ,  H01L27/18 ,  H04J14/02

    摘要： There is described herein a quantum computing system, quantum processor, and method of operating a quantum computing system. The quantum computing system comprises a quantum control system configured for at least one of delivery and receipt of multiplexed optical signals. At least one optical fiber is coupled to the quantum control system for carrying the multiplexed optical signals, and a quantum processor is disposed inside a cryogenics apparatus and coupled to the at least one optical fiber. The quantum processor comprises: at least one converter configured for converting between the multiplexed optical signals and microwave signals at different frequencies; and a plurality of solid-state quantum circuit elements coupled to the at least one converter and addressable by respective ones of the microwave signals at different frequencies.

    Quantum processing apparatus with downsampling analog-to-digital converter
    5.
    发明授权
    Quantum processing apparatus with downsampling analog-to-digital converter 有权

    公开(公告)号：US11621720B2

    公开(公告)日：2023-04-04

    申请号：US17108469

    申请日：2020-12-01

    申请人： International Business Machines Corporation

    发明人： Peter Mueller ,  Thomas Morf ,  Pier Andrea Francese ,  Marcel A. Kossel

    IPC分类号： H03M1/12 ,  G06N10/00 ,  H01L27/18 ,  G01R33/035 ,  H03M1/66 ,  H04B10/70 ,  G06N10/40 ,  G01R33/24 ,  G01N24/12 ,  G01R33/32

    摘要： Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the nth Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the nth Nyquist zone to the mth Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

    Superconducting logic circuits
    6.
    发明授权
    Superconducting logic circuits 有权

    公开(公告)号：US11621714B2

    公开(公告)日：2023-04-04

    申请号：US17486615

    申请日：2021-09-27

    申请人： PsiQuantum Corp.

    发明人： Faraz Najafi

    IPC分类号： H03K19/195 ,  H03K19/20 ,  H01L23/552 ,  H01L39/16 ,  H01L27/18 ,  H01L39/22 ,  H01L31/02 ,  H03K19/23 ,  H01L39/18

    摘要： An electric circuit includes a plurality of superconducting components, each of the plurality of superconducting components having: a respective first terminal; a respective second terminal; and a respective input. The electric circuit further includes a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a bias current adapted to cause the electric circuit to function as a logical OR gate on the respective inputs of the plurality of superconducting components. The electric circuit further includes an output node adapted to output a state of the logical OR gate.

    Low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation
    8.
    发明授权
    Low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation 有权

    公开(公告)号：US11601128B2

    公开(公告)日：2023-03-07

    申请号：US17744107

    申请日：2022-05-13

    申请人： Microsoft Technology Licensing, LLC

    发明人： David J. Reilly

    IPC分类号： H03K19/19 ,  H03K19/195 ,  G06N10/00 ,  G11C11/56 ,  H01L27/11524 ,  H01L27/18

    摘要： Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.

    Superconductive Memory Cells and Devices
    10.
    发明申请
    Superconductive Memory Cells and Devices 有权

    公开(公告)号：US20230055589A1

    公开(公告)日：2023-02-23

    申请号：US17967778

    申请日：2022-10-17

    申请人： PsiQuantum Corp.

    发明人： Faraz Najafi

    IPC分类号： G11C11/44 ,  H01L39/16 ,  H01L27/18 ,  H01L39/08 ,  H01L39/10

    摘要： An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.