公开(公告)号：US20230138732A1

公开(公告)日：2023-05-04

申请号：US18147651

申请日：2022-12-28

申请人： Adeia Semiconductor Inc.

发明人： Javier A. DeLaCruz ,  David Edward Fisch

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L23/00 ,  H01L23/538 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

摘要： A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.

公开(公告)号：US20230132375A9

公开(公告)日：2023-04-27

申请号：US17123413

申请日：2020-12-16

申请人： Texas Instruments Incorporated

发明人： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC分类号： H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

摘要： An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US20230131757A1

公开(公告)日：2023-04-27

申请号：US18088461

申请日：2022-12-23

申请人： Intel Corporation

发明人： Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H10B10/00 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

公开(公告)号：US20230131126A1

公开(公告)日：2023-04-27

申请号：US18088469

申请日：2022-12-23

申请人： Intel Corporation

发明人： Szuya S. LIAO ,  Rahul PANDEY ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Pratik PATEL

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08

摘要： Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US11637176B2

公开(公告)日：2023-04-25

申请号：US17859799

申请日：2022-07-07

申请人： Nuvoton Technology Corporation Japan

发明人： Hironao Nakamura ,  Ryosuke Okawa ,  Tsubasa Inoue ,  Akira Kimura ,  Eiji Yasuda

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/088

摘要： Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm≤Lxr≤0.20 μm holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

公开(公告)号：US20230124961A1

公开(公告)日：2023-04-20

申请号：US18059742

申请日：2022-11-29

申请人： Silanna Asia Pte Ltd

发明人： Vadim Kushner ,  Nima Beikae

IPC分类号： H01L29/06 ,  H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

摘要： A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.

公开(公告)号：US20230121119A1

公开(公告)日：2023-04-20

申请号：US18068718

申请日：2022-12-20

申请人： Bell Semiconductor, LLC

发明人： Nicolas LOUBET ,  Prasanna KHARE

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L27/088 ,  H01L29/49

摘要： A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

公开(公告)号：US20230117590A1

公开(公告)日：2023-04-20

申请号：US17931034

申请日：2022-09-09

申请人： Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd.

发明人： Xiao Yang ,  Hui Chen

IPC分类号： H01L29/10 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

摘要： A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

公开(公告)号：US11631768B2

公开(公告)日：2023-04-18

申请号：US16459511

申请日：2019-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Huang-Siang Lan ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong ,  Hung-Yu Yeh ,  Chung-En Tsai

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

摘要： A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

公开(公告)号：US11631746B2

公开(公告)日：2023-04-18

申请号：US17121385

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L29/08

摘要： A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.