公开(公告)号：US20240365549A1

公开(公告)日：2024-10-31

申请号：US18766417

申请日：2024-07-08

申请人： KIOXIA CORPORATION

发明人： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC分类号： H10B43/27 ,  G11C16/04 ,  H01L29/51 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00

CPC分类号： H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US12133393B2

公开(公告)日：2024-10-29

申请号：US17502380

申请日：2021-10-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Do Young Choi ,  Kab Jin Nam ,  In Bong Pok ,  Dae Won Ha ,  Musarrat Hasan

IPC分类号： H01L27/11592 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/30 ,  H10B51/40

CPC分类号： H10B51/40 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H10B51/30

摘要： A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

公开(公告)号：US20240355892A1

公开(公告)日：2024-10-24

申请号：US18763081

申请日：2024-07-03

申请人： ROHM CO., LTD.

发明人： Yasunobu HAYASHI

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51

CPC分类号： H01L29/4234 ,  H01L29/408 ,  H01L29/51 ,  H01L29/40117

摘要： A semiconductor device includes a planar gate structure including a gate insulating film and a gate electrode, and a sidewall structure disposed adjacent to a lateral side of the planar gate structure. The sidewall structure includes a first insulating film and a second insulating film, and a charge storage film disposed between the first insulating film and the second insulating film. The first insulating film is adjacent to the planar gate structure. A ratio between a gate length L of the planar gate structure and a width WS of the sidewall structure is less than or equal to 300/75. Thereby, a semiconductor device having an improved data read and write reliability in a memory structure can be provided.

公开(公告)号：US12127411B2

公开(公告)日：2024-10-22

申请号：US18363986

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC分类号： H01L29/40 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC分类号： H10B51/30 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US12127410B2

公开(公告)日：2024-10-22

申请号：US17373973

申请日：2021-07-13

申请人： SANDISK TECHNOLOGIES LLC

发明人： Peter Rabkin ,  Masaaki Higashitani

IPC分类号： H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H10B51/30

CPC分类号： H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H10B51/30

摘要： A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.

公开(公告)号：US12124945B2

公开(公告)日：2024-10-22

申请号：US17310203

申请日：2019-01-28

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Hangbing Lv ,  Xiaoxin Xu ,  Qing Luo ,  Ming Liu

IPC分类号： G06N3/065 ,  G11C11/22 ,  G11C11/54 ,  H01L29/51 ,  H01L29/78

CPC分类号： G06N3/065 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/54 ,  H01L29/516 ,  H01L29/78391

摘要： Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

公开(公告)号：US20240347340A1

公开(公告)日：2024-10-17

申请号：US18299610

申请日：2023-04-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

发明人： Shu-Jui CHANG ,  Shin-Yuan WANG ,  Yu-Che HUANG ,  Chao-Hsin CHIEN ,  Chenming HU

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51

CPC分类号： H01L21/20 ,  H01L21/02175 ,  H01L21/76829 ,  H01L29/41725 ,  H01L29/516

摘要： An epitaxial structure includes a substrate and a dielectric layer. The dielectric layer is on the substrate. The substrate comprises a single crystal metal or a single crystal 2D material. The dielectric layer is in physical contact with the substrate. The dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (FE) phase or antiferroelectric (AFE) phase.

公开(公告)号：US12120883B2

公开(公告)日：2024-10-15

申请号：US17666448

申请日：2022-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Yong Park ,  Jin-Hong Park ,  Sungjoo Lee

IPC分类号： H10B51/20 ,  H01L29/51 ,  H01L29/78 ,  H10B51/30

CPC分类号： H10B51/20 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/30

摘要： A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

公开(公告)号：US12120866B2

公开(公告)日：2024-10-15

申请号：US17731431

申请日：2022-04-28

申请人： SK hynix Inc.

发明人： Jun Sik Kim

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H10B12/00

CPC分类号： H10B12/30 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B12/03 ,  H10B12/05

摘要： Present invention relates to a highly-integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, a semiconductor device comprises: an active layer including a channel, the active layer being spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode; and a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer.

公开(公告)号：US20240339519A1

公开(公告)日：2024-10-10

申请号：US18747379

申请日：2024-06-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： YING-CHIH CHEN ,  BLANKA MAGYARI-KOPE

IPC分类号： H01L29/51 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L28/55 ,  H01L28/60 ,  H01L29/516 ,  H01L29/78391

摘要： A device includes a gate stack and a channel layer over the gate stack. The gate stack includes a metal gate electrode, a ferroelectric layer, and a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode. The semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm.