公开(公告)号：US07064395B2

公开(公告)日：2006-06-20

申请号：US10788379

申请日：2004-03-01

申请人： Takayoshi Minami ,  Yuji Setta

发明人： Takayoshi Minami ,  Yuji Setta

IPC分类号： H01L29/76 ,  H01L29/54 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76895 ,  H01L21/823871 ,  H01L27/11 ,  H01L27/1104

摘要： The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

摘要翻译： 半导体器件包括栅极互连24a，栅极互连24a包括形成在半导体衬底14上的栅电极，其间形成有栅极绝缘膜22; 形成在栅极互连24a的端部附近的第一源极/漏极扩散层28; 远离栅极互连24a和第一源极/漏极扩散层28形成的第二源极/漏极扩散层34; 以及形成在栅极互连件24a上的绝缘膜40，第一源极/漏极扩散层28和第二源极/漏极扩散层34，并且具有形成在其中的沟槽形开口42a，其一体地露出栅极互连24 第一源极/漏极扩散层28中的一个和第二源极/漏极扩散层34中的一个; 以及埋在槽形开口部分41a中的接触层48a。 可以形成用于埋入的接触层48a的槽形开口部41a，而不会发生故障。 因此，可以提供一种能够实现微粉化而不降低可靠性并降低制造成品率的半导体器件。

公开(公告)号：US5864149A

公开(公告)日：1999-01-26

申请号：US842770

申请日：1997-04-17

申请人： Shuki Yamamori

发明人： Shuki Yamamori

IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786 ,  H01L29/54 ,  H01L29/78

CPC分类号： H01L29/66765 ,  H01L29/458 ,  Y10S148/053

摘要： A multi-layer structure of source/drain electrodes and an amorphous silicon layer in a forward staggered thin film transistor. Source/drain electrodes are selectively provided on an insulator. Each of the source/drain electrodes comprises an undoped transparent conductive film on the insulator and an impurity doped transparent conductive film extending over the undoped transparent conductive film. An amorphous silicon active layer extends over the source/drain electrodes and a top surface of the insulator so that the amorphous silicon active layer over the source/drain electrodes has an impurity diffused interface in contact with the impurity doped transparent conductive film to form ohmic contacts between the impurity doped transparent conductive film and the amorphous silicon active layer. The amorphous silicon active layer in contact with the top surface of the insulator between the source/drain electrodes is free of impurities.

摘要翻译： 在前交错薄膜晶体管中的源/漏电极和非晶硅层的多层结构。 源/漏电极选择性地设置在绝缘体上。 源/漏电极中的每一个包括在绝缘体上的未掺杂的透明导电膜和在未掺杂的透明导电膜上延伸的掺杂杂质的透明导电膜。 非晶硅有源层在源极/漏极电极和绝缘体的顶表面上延伸，使得源极/漏极上的非晶硅有源层具有与杂质掺杂的透明导电膜接触的杂质扩散界面，以形成欧姆接触 在杂质掺杂的透明导电膜和非晶硅有源层之间。 与源极/漏极之间的绝缘体的顶表面接触的非晶硅有源层没有杂质。

公开(公告)号：US5677557A

公开(公告)日：1997-10-14

申请号：US742129

申请日：1996-10-31

申请人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/76 ,  H01L31/113 ,  H01L29/54 ,  H01L31/262

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

摘要翻译： 实现了一种用于多晶硅层互连的埋地金属插塞结构的制造方法以及用于同时制造诸如DRAM和SRAM的半导体集成电路上的金属插头的方法。 该方法涉及在图案化的多晶硅层中的开口上形成绝缘层中的接触开口。 多晶硅层中的开口对准衬底上的源/漏接触区域，并提供用于形成自对准接触开口的装置。 接触开口中埋入的金属塞形成多晶硅层与源极/漏极之间的互连。 并且，通过合并工艺步骤，同时形成用于触点的金属插头互连件到半导体器件和第一级金属。 该过程适用于在DRAM和SRAM电路上形成位线触点，同时在芯片上形成周边触点。

公开(公告)号：US5506452A

公开(公告)日：1996-04-09

申请号：US287781

申请日：1994-08-09

申请人： Reinhold Kuhnert

发明人： Reinhold Kuhnert

IPC分类号： H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L23/492 ,  H01L25/04 ,  H01L25/18 ,  H01L29/54 ,  H01L23/18

CPC分类号： H01L23/4928 ,  H01L23/051 ,  H01L23/4922 ,  H01L24/72 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/19043

摘要： A power semiconductor component includes a semiconductor body having anode and cathode sides and a given thermal coefficient of expansion. Contact electrodes are each disposed on a respective one of the anode and cathode sides and are made of a metal having a thermal coefficient of expansion differing from the given thermal coefficient of expansion. At least two contact surfaces are disposed one above the other under pressure, between the semiconductor body and the contact electrodes. At least one of the contact surfaces has a layer formed of an amorphous carbon-metal compound.

摘要翻译： 功率半导体元件包括具有阳极和阴极侧面以及给定的热膨胀系数的半导体本体。 接触电极各自设置在阳极侧和阴极侧的相应一个上，并且由具有与给定的热膨胀系数不同的膨胀热膨胀系数的金属制成。 在半导体本体和接触电极之间的压力下，至少两个接触表面一个在另一个之上设置。 至少一个接触表面具有由无定形碳 - 金属化合物形成的层。

公开(公告)号：US5468991A

公开(公告)日：1995-11-21

申请号：US158740

申请日：1993-11-30

申请人： Joon K. Lee ,  Hyeon J. Jeong

发明人： Joon K. Lee ,  Hyeon J. Jeong

IPC分类号： H01L21/56 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48 ,  H01L29/43 ,  H01L29/54

CPC分类号： H01L23/4951 ,  H01L2924/0002

摘要： A lead frame for a semiconductor device used in a vertically surface-mounted package which has internal leads gathered on one side thereof includes separately formed dummy leads attached to a semiconductor chip on the opposite side of the lead frame to avoid an inconsistent inflow pressure of a molding material during a package molding process caused by gathering of the internal leads on only one side, thereby enhancing reliability of the semiconductor package. There is also no need to separately form a heat sink structure for eliminating heat of the semiconductor chip since the dummy leads function as the heat sink.

摘要翻译： 用于垂直表面安装封装的半导体器件的引线框架，其具有聚集在其一侧上的内部引线，包括附接到引线框架相对侧上的半导体芯片的单独形成的虚拟引线，以避免引线框架的不一致的流入压力 在封装成型过程中由内部引线聚集在一侧引起的成型材料，从而提高半导体封装的可靠性。 由于虚设引线用作散热器，因此也不需要分开形成用于消除半导体芯片的热量的散热器结构。

公开(公告)号：US5451819A

公开(公告)日：1995-09-19

申请号：US71387

申请日：1993-06-02

申请人： Kuniaki Koyama

发明人： Kuniaki Koyama

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/45 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L2924/0002

摘要： A semiconductor device adapted for reduction in size and increasing density is disclosed. The semiconductor device comprises an insulating layer having therein a contact hole in which a first conductive layer or a contact electrode is deposited for connecting a semiconductor active region with an overlying second conductive layer. The contact electrode has a top portion protruding from the insulating layer and a side surface in contact with the second conductive layer for increasing a contact area between the contact electrode and the second conductive layer. The top surface of the contact electrode may be provided with an insulating layer between the top surface and the interconnection wiring layer formed from the second conductive layer in order to avoid etching of the contact electrode and underlying semiconductor active region during etching of the second conductive layer, even in the case of misalignment of the contact electrode with the interconnection wiring layer.

摘要翻译： 公开了一种适于减小尺寸和增加密度的半导体器件。 半导体器件包括其中具有接触孔的绝缘层，其中沉积有第一导电层或接触电极，用于将半导体有源区与上覆的第二导电层连接。 接触电极具有从绝缘层突出的顶部部分和与第二导电层接触的侧表面，用于增加接触电极和第二导电层之间的接触面积。 接触电极的顶表面可以在顶表面和由第二导电层形成的互连布线层之间设置绝缘层，以避免在蚀刻第二导电层期间蚀刻接触电极和下面的半导体有源区 即使在接触电极与互连布线层未对准的情况下也是如此。

公开(公告)号：US5448113A

公开(公告)日：1995-09-05

申请号：US352856

申请日：1994-12-02

申请人： Kouei Suzuki ,  Kouichi Ohtaka ,  Ikue Kawashima ,  Shuichi Hikichi

发明人： Kouei Suzuki ,  Kouichi Ohtaka ,  Ikue Kawashima ,  Shuichi Hikichi

IPC分类号： H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC分类号： H01L23/5329 ,  H01L23/53214 ,  H01L2924/0002

摘要： A micro metal-wiring construction comprises a substrate having a first insulating layer thereon, a metal wiring formed on the first insulating layer of the substrate, and a second insulating layer covering the metal wiring. The coefficient of thermal expansion of the metal wiring is greater than those of the first and the second insulating layers. Intersection lines formed between grain boundaries of the metal wiring and a surface of the first insulating layer is nearly perpendicular to an extending direction of the metal wiring and an angle between grain boundary planes and a line that is perpendicular to a surface of the first insulating layer is greater than 20 degrees. Metal-wiring having a good resistance against stress-induced-migration is obtained by providing when this angle is greater than 20.degree..

摘要翻译： 微金属布线结构包括其上具有第一绝缘层的基板，形成在基板的第一绝缘层上的金属布线和覆盖金属布线的第二绝缘层。 金属布线的热膨胀系数大于第一和第二绝缘层的热膨胀系数。 在金属布线的晶界与第一绝缘层的表面之间形成的交叉线与金属布线的延伸方向大致垂直，并且晶界平面与垂直于第一绝缘层表面的线之间的角度 大于20度。 当该角度大于20°时，可以获得具有良好抗应力诱导迁移性的金属布线。

公开(公告)号：US5418397A

公开(公告)日：1995-05-23

申请号：US234512

申请日：1994-04-28

申请人： Toshiaki Ogawa

发明人： Toshiaki Ogawa

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L21/02071

摘要： Disclosed is a method of forming an interconnection pattern which causes no disconnection even when making contact with water in the atmosphere. An interconnection layer is formed on a semiconductor substrate. The interconnection layer is selectively etched by employing a halogen-type gas, to form an interconnection pattern. Ultraviolet rays are directed onto the interconnection pattern in the atmosphere including a hydrogen gas. This method avoids generation of hydrogen halogenide which causes corrosion of metal interconnections even when the metal interconnections make contact with water in the atmosphere, thereby to prevent disconnections of the metal interconnections.

摘要翻译： 公开了一种形成互连图案的方法，即使在与大气中的水接触时也不会断开连接。 在半导体衬底上形成互连层。 通过使用卤素型气体选择性地蚀刻互连层，以形成互连图案。 在包括氢气的大气中的紫外线被引导到互连图案上。 该方法即使当金属互连与大气中的水接触时也避免产生卤化氢，导致金属互连的腐蚀，从而防止金属互连的断开。

公开(公告)号：US5410174A

公开(公告)日：1995-04-25

申请号：US102529

申请日：1993-08-04

申请人： Alexander Kalnitsky

发明人： Alexander Kalnitsky

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/74 ,  H01L21/768 ,  H01L23/485 ,  H01L29/54

CPC分类号： H01L21/743

摘要： A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. a conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer. The first and second silicon layers are then etched to form a conductive structure contacting the exposed portion of the substrate through the etch stop layer.

摘要翻译： 提供一种用于形成集成电路的多晶硅埋入触点的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成场氧化物区域，留下暴露的有源区。 在有源区上形成氧化物层。 在第一硅层上形成并图案化第一光致抗蚀剂层。 然后蚀刻第一硅层以形成其中的开口以暴露氧化物层的一部分。 通过开口蚀刻氧化物层以暴露基板的一部分。 在衬底和第一光致抗蚀剂层的暴露部分之上形成导电蚀刻停止层。 然后去除覆盖在第一光致抗蚀剂层上的第一光致抗蚀剂层和蚀刻停止层。 在第一硅层和剩余的蚀刻停止层上形成第二硅层。 在第二硅层上形成并图案化第二光致抗蚀剂层。 然后蚀刻第一和第二硅层以形成通过蚀刻停止层接触衬底的暴露部分的导电结构。

公开(公告)号：US5402005A

公开(公告)日：1995-03-28

申请号：US291037

申请日：1994-08-15

申请人： Kohichi Takayama ,  Masanori Kinugasa ,  Munenobu Kida ,  Shuichi Shoji

发明人： Kohichi Takayama ,  Masanori Kinugasa ,  Munenobu Kida ,  Shuichi Shoji

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002

摘要： At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.

摘要翻译： 在形成在基板上的下布线层的接触区域周围形成具有预定形状的至少一个狭缝，并且与该绝缘层一体形成的绝缘部分嵌入该狭缝中。 该绝缘层形成在下布线层上，并具有位于与接触区域对应的位置的接触孔。 由于作为矩形突起部分的绝缘部分从刚性绝缘层向下突出到狭缝中，所以可以抑制由上部布线层的退火中的下部布线层的热膨胀引起的位置误差，以及诸如突起 可以防止在上部布线层上。 此外，可以获得没有相互连接短路并且具有优异的平坦度的半导体器件。