公开(公告)号：US20240282661A1

公开(公告)日：2024-08-22

申请号：US18173033

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chien Pan ,  Yu-Wei Lin ,  Pu Wang ,  Li-Hui Cheng

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L29/68

CPC classification number: H01L23/373 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/97 ,  H01L25/072 ,  H01L29/685 ,  H01L2224/32225 ,  H01L2224/97 ,  H01L2924/1434

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package includes a substrate, and first, second and third semiconductor elements disposed on and electrically connected to the substrate. A heat transfer enhancing layer, a thermal conductive material layer and an adhesive material layer are respectively disposed on and joined to the first, second and third semiconductor elements. A lid is disposed over the first, second and third semiconductor elements, and joined to the heat transfer enhancing layer, the thermal conductive material layer and the adhesive material layer. The thermal conductive material layer has a thermal conductivity lower than that of the heat transfer enhancing layer and higher than that of the adhesive material layer, and the thermal conductive material layer has a bonding strength larger than that of the heat transfer enhancing layer and smaller than that of the adhesive material layer.

公开(公告)号：US12027628B2

公开(公告)日：2024-07-02

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/68 ,  H01L29/76

CPC classification number: H01L29/78645 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US20240063296A1

公开(公告)日：2024-02-22

申请号：US18220868

申请日：2023-07-12

Applicant: Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： GUANG-QI ZHANG ,  YANG WEI ,  SHOU-SHAN FAN

IPC: H01L29/68 ,  H03K19/08 ,  H01L29/24 ,  H01L29/76

CPC classification number: H01L29/685 ,  H03K19/08 ,  H01L29/24 ,  H01L29/7606

Abstract: The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

公开(公告)号：US11469314B1

公开(公告)日：2022-10-11

申请号：US17412485

申请日：2021-08-26

Applicant: Korea University Research and Business Foundation

Inventor： Sang Sig Kim ,  Kyoung Ah Cho ,  Doo Hyeok Lim

IPC: H01L29/68 ,  H03K19/1776

Abstract: The present disclosure relates to a reconfigurable logic-in-memory device using a silicon transistor, according to the embodiment of the present disclosure, the reconfigurable logic-in-memory device using a silicon transistor comprises the silicon transistor including a drain region, a first channel region, a second channel region, a source region, and a gate region, wherein the silicon transistor performs a first channel operation while forming a first positive feedback loop in which an electron is a majority carrier in the first channel region and the second channel region depending on a level of a gate voltage Vin applied through the gate region or performs a second channel operation while forming a second positive feedback loop in which a hole is a majority carrier in the first channel region and the second channel region depending on the level of a gate voltage Vin applied through the gate region.

公开(公告)号：US20210098611A1

公开(公告)日：2021-04-01

申请号：US17036428

申请日：2020-09-29

Applicant: NORTHWESTERN UNIVERSITY

Inventor： Mark C. Hersam ,  Vinod K. Sangwan ,  Hong-Sub Lee

IPC: H01L29/68 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/739 ,  G06N3/04 ,  G06N3/08

Abstract: A memtransistor includes a top gate electrode and a bottom gate electrode; a polycrystalline monolayer film formed of an atomically thin material disposed between the top gate electrode and the bottom gate electrode; and source and drain electrodes spatial-apart formed on the polycrystalline monolayer film to define a channel in the polycrystalline monolayer film between the source and drain electrodes. The top gate electrode and the bottom gate electrode are capacitively coupled with the channel.

公开(公告)号：US10153764B2

公开(公告)日：2018-12-11

申请号：US15377750

申请日：2016-12-13

Applicant: Infineon Technologies AG

Inventor： Markus Bina ,  Jens Barrenscheen ,  Anton Mauder

IPC: H03K3/00 ,  H03K17/56 ,  G01R19/00 ,  H01L49/02 ,  H01L29/68

Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.

公开(公告)号：US10141407B2

公开(公告)日：2018-11-27

申请号：US14506041

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： David Seo ,  Ho-jung Kim ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Seong-ho Cho

IPC: H01L27/108 ,  H01L29/66 ,  H01L45/00 ,  H01L29/16 ,  H01L29/68 ,  H01L27/105 ,  H01L29/76

Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

公开(公告)号：US09691756B2

公开(公告)日：2017-06-27

申请号：US13750387

申请日：2013-04-22

Applicant: Euipil Kwon

Inventor： Euipil Kwon

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/84 ,  H01L29/68 ,  H01L27/102 ,  H01L29/861 ,  H01L27/112 ,  H01L29/872 ,  H01L27/12 ,  H01L29/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/04

CPC classification number: H01L27/0629 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/0466 ,  G11C2207/005 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/685 ,  H01L29/8611 ,  H01L29/872

Abstract: The nonvolatile memory device includes a memory cell having a transistor in which an insulating isolation layer is formed in a channel region. The nonvolatile memory device includes a metal-oxide-semiconductor (MOS) transistor as a basic component. An insulating isolation layer is formed in at least a channel region, and a gate insulating layer includes an insulating layer or a variable resistor and serves as a data storage. A gate includes a metal layer formed in a lower portion thereof. First source and drain regions are lightly doped with a dopant, and second source and drain regions are heavily doped with a dopant.

公开(公告)号：US09679983B2

公开(公告)日：2017-06-13

申请号：US14613897

申请日：2015-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mueng-Ryul Lee ,  Sang-Bae Yi

IPC: H01L29/68 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66621 ,  H01L29/7827 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate including isolation regions defining first and second active regions having a first and second conductivity type, respectively, first threshold voltage control regions in predetermined regions of the first active region, wherein the first threshold voltage control regions have the first conductivity type and a different impurity concentration from the first active region, a first gate trench extending across the first active region, wherein portions of side bottom portions of the first gate trench adjacent to the respective isolation region are disposed at a higher level than a central bottom portion of the first gate trench, and the first threshold voltage control regions remain in the first active region under the side bottom portions of the first gate trench adjacent to the respective isolation region, and a first gate pattern. Methods of manufacturing such semiconductor devices are also provided.

公开(公告)号：US09627208B2

公开(公告)日：2017-04-18

申请号：US14842405

申请日：2015-09-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsushi Ishimaru ,  Masami Nagaoka

IPC: H03K17/16 ,  H03K17/81 ,  H01L23/62 ,  H01L29/68 ,  H01L21/263

CPC classification number: H01L21/263 ,  H01L27/1203 ,  H01L27/124

Abstract: According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film.