BIPOLAR TRANSISTORS
    2.
    发明申请

    公开(公告)号:US20230087058A1

    公开(公告)日:2023-03-23

    申请号:US17549013

    申请日:2021-12-13

    IPC分类号: H01L29/732 H01L29/66

    摘要: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

    MODULAR GUIDED KEEPER BASE
    3.
    发明申请

    公开(公告)号:US20230084734A1

    公开(公告)日:2023-03-16

    申请号:US17990873

    申请日:2022-11-21

    摘要: A modular guided keeper base, guided keeper assembly, and related method includes a modular guided keeper base that mounts to a die member. The guided keeper base has an integrated stop for guide pin retention. The guided keeper base can also accommodate a variety of bushings within the base. The guided keeper base is attached to a die member using a mounting flange(s). Mounting fasteners pass through the fastener holes in the mounting flanges and are anchored in the die member to securely retain the guided keeper assembly in place. A retainer ring is mounted in an associated groove in the base over the heads of the mounting fasteners to prevent unintentional unfastening of the fasteners from the die member.

    METHOD AND SYSTEM OF OPERATING A BI-DIRECTIONAL DOUBLE-BASE BIPOLAR JUNCTION TRANSISTOR (B-TRAN)

    公开(公告)号:US20220190115A1

    公开(公告)日:2022-06-16

    申请号:US17537726

    申请日:2021-11-30

    申请人: IDEAL POWER INC.

    摘要: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.