公开(公告)号：US20250063770A1

公开(公告)日：2025-02-20

申请号：US18451096

申请日：2023-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Tung-Ying Lee ,  Yu-Chao Lin

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.

公开(公告)号：US12218242B2

公开(公告)日：2025-02-04

申请号：US18336005

申请日：2023-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Lien Huang

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A semiconductor structure includes at least a fin structure, a gate structure over the fin structure, a connecting structure, a first dielectric structure over the gate structure, and a second dielectric structure. The fin structure extends in a first direction, and the gate structure extends in a second direction different from the first direction. The connecting structure is disposed over the fin structure and isolated from the gate structure. The second dielectric structure extends in the first direction. The first dielectric structure and the second dielectric structure include a same material. A top surface of the first dielectric structure and a top surface of the second dielectric structure are substantially aligned with each other.

公开(公告)号：US12211931B2

公开(公告)日：2025-01-28

申请号：US17814620

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/78

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

公开(公告)号：US20250022943A1

公开(公告)日：2025-01-16

申请号：US18352833

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Shih-Yen LIN ,  Po-Cheng TSAI ,  Che-Jia CHANG

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a 2-D material channel layer, a gate structure, and source/drain electrodes. The gate structure is over a channel region of the 2-D material channel layer. The source/drain electrodes are over source/drain regions of the 2-D material channel layer, respectively. Each of the source/drain electrodes includes a 2-D material electrode and a metal electrode. The 2-D material electrode is below a bottom surface of a corresponding one of the source/drain regions of the 2-D material channel layer. The metal electrode is over a top surface of the corresponding one of the source/drain regions of the 2-D material channel layer.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US12176035B2

公开(公告)日：2024-12-24

申请号：US17583651

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H01L29/76 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.

公开(公告)号：US20240395885A1

公开(公告)日：2024-11-28

申请号：US18667967

申请日：2024-05-17

Applicant: TAI & SONS INDUSTRIAL CO., LTD.

Inventor： Ming-Hsiu TSAI ,  Chih-Ting LIN ,  Kuan-Chou LIN

IPC: H01L29/423 ,  H01L27/12 ,  H01L29/16 ,  H01L29/417 ,  H01L29/76

Abstract: A graphene optical device includes a base, a plurality of graphene transistors, and an electrical connection structure. Each of the graphene transistors includes a graphene layer, a metal nanoparticle layer, an insulation layer, a polymer electrolyte layer, and an electrode unit. The electrode unit includes a source electrode, a drain electrode, a first gate electrode component which includes a plurality of first gate electrodes, and a second gate electrode component which includes a plurality of second gate electrodes. The insulation layer has an opening. The polymer electrolyte layer is disposed between the metal nanoparticle layer exposed from the opening and the first gate electrodes, and between the metal nanoparticle layer exposed from the opening and the second gate electrodes. The electrical connection includes a source electrode connecting unit, a drain electrode connecting unit, a first gate electrode connecting unit, and a second gate electrode connecting unit.

公开(公告)号：US12154828B2

公开(公告)日：2024-11-26

申请号：US17575147

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  National Yang Ming Chiao Tung University

Inventor： Chiung-Yuan Lin ,  Tsung-Fu Yang ,  Weicheng Chu ,  Ching Liang Chang ,  Chen Han Chou ,  Chia-Ho Yang ,  Tsung-Kai Lin ,  Tsung-Han Lin ,  Chih-Hung Chung ,  Chenming Hu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.

公开(公告)号：US12148826B2

公开(公告)日：2024-11-19

申请号：US18383461

申请日：2023-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

公开(公告)号：US12142608B2

公开(公告)日：2024-11-12

申请号：US18308229

申请日：2023-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Yu Chou ,  Yi-Ting Fu ,  Ting-Gang Chen ,  Tze-Liang Lee

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.