公开(公告)号：US20240332322A1

公开(公告)日：2024-10-03

申请号：US18129407

申请日：2023-03-31

申请人： Intel Corporation

发明人： Srinivasan Raman ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Kripa Chauhan

IPC分类号： H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66 ,  H01L29/772

CPC分类号： H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66409 ,  H01L29/772

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

公开(公告)号：US20240178830A1

公开(公告)日：2024-05-30

申请号：US18070585

申请日：2022-11-29

申请人： Infineon Technologies Austria AG

发明人： Kennith Kin Leong

IPC分类号： H03K17/08 ,  H01L27/02 ,  H01L29/772 ,  H01L29/866

CPC分类号： H03K17/08 ,  H01L27/0255 ,  H01L29/772 ,  H01L29/866

摘要： A power semiconductor device includes: a main power switch having a drain, source, and gate; and a voltage clamp circuit in parallel with the main power switch and having a clamp voltage less than a breakdown voltage of the main power switch. The voltage clamp circuit includes: a pulldown switch having a normally-on gate electrically connected to the source of the main power switch; a plurality of series-connected diodes electrically connected between the drain of the main power switch and a drain of the pulldown switch; a voltage clamp device electrically connected between a source of the pulldown switch and the source of the main power switch; and a second power switch having a normally-off gate electrically connected to the drain of the pulldown switch, a drain electrically connected to the drain of the main power switch, and a source electrically connected to the source of the pulldown switch.

公开(公告)号：US20220085188A1

公开(公告)日：2022-03-17

申请号：US17103876

申请日：2020-11-24

申请人： Bo TU ,  Hsiang-Yi CHENG

发明人： Bo TU ,  Hsiang-Yi CHENG

IPC分类号： H01L29/66 ,  H01L29/772 ,  H01L49/02

摘要： The present invention discloses a stacked semiconductor chip structure and its process wherein the stacked semiconductor chip structure comprises a substrate as well as P-type semiconductor layers and N-type semiconductor layers which are stacked one by one on the substrate, wherein the P-type semiconductor layers and the N-type semiconductor layers are arranged alternately, there are at least two P-type semiconductor layers and at least two N-type semiconductor layers. The present invention uses the chemical vapor deposition method to stack and form the P-type semiconductor layers and the N-type semiconductor layers, uses the physical etching and the plasma cleaning to form the conducting layers and thus avoids using the photo masks, the photo resist and the mask aligners for the manufacture of semiconductor chips, reduces the complexity of semiconductor chip processes and increases the yield of semiconductor chip products.

公开(公告)号：US20220076108A1

公开(公告)日：2022-03-10

申请号：US17416765

申请日：2019-11-07

申请人： IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

发明人： Jea Gun PARK ,  Jong Ung BAEK

IPC分类号： G06N3/063 ,  H01L29/772

摘要： The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a two-terminal spin device for performing integration and fire, and the two-terminal spin device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

公开(公告)号：US11069781B2

公开(公告)日：2021-07-20

申请号：US16534318

申请日：2019-08-07

申请人： FLOSFIA INC.

发明人： Toshimi Hitora ,  Masaya Oda ,  Akio Takatsuka

IPC分类号： H01L29/24 ,  H01L21/02 ,  H01L29/66 ,  H01L29/772 ,  H01L29/808 ,  H01L29/78 ,  H01L29/872 ,  H01L29/04 ,  H01L29/739 ,  H01L29/778 ,  H01L29/812 ,  H01L33/44 ,  H01L33/26 ,  H01L33/00

摘要： A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

公开(公告)号：US10593673B2

公开(公告)日：2020-03-17

申请号：US15980250

申请日：2018-05-15

申请人： International Business Machines Corporation

发明人： Xin Miao ,  Jingyun Zhang ,  Alexander Reznicek ,  Choonghyun Lee

IPC分类号： H01L29/00 ,  H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L29/772 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/161 ,  H01L29/786 ,  H01L21/8232

摘要： A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

公开(公告)号：US10553713B2

公开(公告)日：2020-02-04

申请号：US15286055

申请日：2016-10-05

申请人： ROHM CO., LTD.

发明人： Yuki Nakano

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/04

摘要： The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y≤9×10−7x2−0.0004x+0.7001  (1).

公开(公告)号：US10449573B2

公开(公告)日：2019-10-22

申请号：US15634137

申请日：2017-06-27

申请人： Johan Calcoen ,  Peter Stulens

发明人： Johan Calcoen ,  Peter Stulens

IPC分类号： B07C5/36 ,  H01L31/024 ,  B07C5/34 ,  G01J1/42 ,  G01J1/44 ,  H01L25/16 ,  H01L31/107 ,  B07C5/342 ,  G01J1/02 ,  H01L29/772

摘要： A sorting apparatus is described and which includes a selectively heated avalanche photodiode (APD) which is maintained at a predetermined temperature and which further demonstrates a higher gain and signal-to-noise ratio with greater stability at a predetermined temperature for enhancing sorting efficiency.

公开(公告)号：US10276703B2

公开(公告)日：2019-04-30

申请号：US15619679

申请日：2017-06-12

申请人： FUJITSU LIMITED

发明人： Youichi Kamada ,  Shirou Ozaki

IPC分类号： H01L29/772 ,  H01L29/778 ,  H01L29/66 ,  H01L23/29 ,  H01L23/31 ,  H01L29/423 ,  H01L29/20

摘要： A compound semiconductor device includes: a carrier transit layer; a carrier supply layer over the carrier transit layer; a source electrode and a drain electrode above the carrier supply layer; a gate electrode above the carrier supply layer between the source electrode and the drain electrode; and a first insulating film and a second insulating film above the carrier supply layer between the gate electrode and the drain electrode. The gate electrode includes a portion above the second insulating film, the second insulating film covers a side surface of the first insulating film from the drain electrode side, and a second concentration of electron traps in the second insulating film is higher than a first concentration of electron traps in the first insulating film.

公开(公告)号：US10269802B2

公开(公告)日：2019-04-23

申请号：US14714231

申请日：2015-05-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chih-Han Lin

IPC分类号： H01L29/772 ,  H01L27/092 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3213

摘要： A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.