-
公开(公告)号：US20240365528A1
公开(公告)日：2024-10-31
申请号：US18643224
申请日：2024-04-23
发明人： Changhoon SUNG , Hyojin Cho , Hoyoung Tang , Taehyung Kim , Eojin Lee
IPC分类号： H10B10/00 , G11C5/06 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H10B10/125 , G11C5/063 , H01L23/5283 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.
-
公开(公告)号：US20240363725A1
公开(公告)日：2024-10-31
申请号：US18309125
申请日：2023-04-28
发明人： Yu-Ling Hsieh , Hung-Ju Chou , Yu-Shan Lu , Wei-Yang Lee , Chih-Chung Chang , Yao-Hsuan Lai
IPC分类号： H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775
CPC分类号： H01L29/66439 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/775
摘要： Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.
-
公开(公告)号：US20240363724A1
公开(公告)日：2024-10-31
申请号：US18307025
申请日：2023-04-26
发明人： Ding-Kang Shih
IPC分类号： H01L29/66 , H01L21/02 , H01L21/311 , H01L21/768 , H01L23/535 , H01L29/06 , H01L29/423 , H01L29/775
CPC分类号： H01L29/66439 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02532 , H01L21/31111 , H01L21/76895 , H01L23/535 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/775
摘要： A method of manufacturing a semiconductor device includes: forming a stack of semiconductor layers and sacrificial layers alternately arranged over a substrate; patterning the stack to form a stacking structure on the substrate; disposing a sacrificial gate structure on the substrate, where the sacrificial gate structure covers a portion of the stacking structure; removing portions of the stacking structure not overlapped with the sacrificial gate structure; disposing source/drain regions at opposite sides of the sacrificial gate structure, where the semiconductor layers in the remained stacking structure connect between the source/drain regions; removing the sacrificial gate structure and rest of the sacrificial layers to form a cavity accessibly revealing the semiconductor layers; forming a semiconductor material to cover the semiconductor layers; performing a thermal process to transfer the semiconductor material into a Si-containing layer and a Ge-containing layer, where the Si-containing layer is disposed over the semiconductor layers, and the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers; and forming a gate structure in the cavity and over the remained stacking structure.
-
公开(公告)号：US20240363701A1
公开(公告)日：2024-10-31
申请号：US18492327
申请日：2023-10-23
发明人： Jongryeol Yoo
IPC分类号： H01L29/417 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： The present disclosure relates to semiconductor devices and their fabrication methods. One example semiconductor device comprises a substrate that includes an active region, an active pattern on the active region, a source/drain pattern on the active pattern, an active contact that extends from a top surface to a sidewall of the source/drain pattern and includes a first part that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern, a first layer between the source/drain pattern and the first part, and a second layer separated from the first layer and across the first part. Each of the first layer and the second layer includes a silicide layer.
-
公开(公告)号：US20240363690A1
公开(公告)日：2024-10-31
申请号：US18306421
申请日：2023-04-25
发明人： Haining Yang , Ming-Huei Lin , Junjing Bao
IPC分类号： H01L29/10 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/1054 , H01L21/823807 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.
-
公开(公告)号：US20240363684A1
公开(公告)日：2024-10-31
申请号：US18308912
申请日：2023-04-28
发明人： Chun-Yuan CHEN , Lo-Heng CHANG , Huan-Chieh SU , Chih-Hao WANG , Szu-Chien WU
IPC分类号： H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.
-
7.发明公开公开(公告)号：US20240363532A1
公开(公告)日：2024-10-31
申请号：US18626985
申请日：2024-04-04
发明人： Seungyoung Lee , Jungho Do
IPC分类号： H01L23/528 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/5283 , H01L23/5226 , H01L27/092 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An integrated circuit includes a standard cell including a first transistor and a second transistor each disposed on a front side of a substrate, a backside via passing through the substrate in a vertical direction with respect to the substrate, a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected with a first source/drain of the first transistor through the backside via, and a backside contact extending in a first direction between the standard cell and the backside wiring layer and electrically connecting a second source/drain of the first transistor with a first source/drain of the second transistor, wherein a bottom level of the backside contact differs from a top level of the backside power rail, and the backside contact is electrically insulated from the backside power rail.
-
公开(公告)号：US20240363531A1
公开(公告)日：2024-10-31
申请号：US18626935
申请日：2024-04-04
发明人： Soyeon Kim , Hoyoung Tang , Taehyung Kim
IPC分类号： H01L23/528 , G11C5/06 , G11C11/419 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786 , H10B10/00
CPC分类号： H01L23/5283 , G11C5/063 , G11C11/419 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7851 , H01L29/78696 , H10B10/125
摘要： Provided is an integrated circuit including a cell array disposed on a substrate and including a plurality of bit cells, a row decoder including a plurality of word line drivers each providing a plurality of word line signals to the cell array, a backside wiring layer disposed on a back side of the substrate to overlap the row decoder and providing power to the plurality of word line drivers, and a plurality of backside contacts between the row decoder and the backside wiring layer. Each of the plurality of backside contacts extends from a source of at least one transistor included in each of the plurality of word line drivers to the backside wiring layer.
-
公开(公告)号：US12132000B2
公开(公告)日：2024-10-29
申请号：US17460168
申请日：2021-08-28
发明人： Shao-Kuan Lee , Cheng-Chin Lee , Cherng-Shiaw Tsai , Kuang-Wei Yang , Hsin-Yen Huang , Hsiaokang Chang , Shau-Lin Shue
IPC分类号： H01L23/532 , H01L21/768 , H01L23/522 , H01L23/535 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/775 , H01L29/786
CPC分类号： H01L23/53276 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L23/535 , H01L29/0665 , H01L29/0673 , H01L29/401 , H01L29/41733 , H01L29/42392 , H01L29/45 , H01L29/775 , H01L29/78618 , H01L29/78696
摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed adjacent the second conductive feature, a first dielectric material disposed between the second and third conductive features, a first one or more graphene layers disposed between the second conductive feature and the first dielectric material, and a second one or more graphene layers disposed between the third conductive feature and the first dielectric material.
-
公开(公告)号：US20240355907A1
公开(公告)日：2024-10-24
申请号：US18456241
申请日：2023-08-25
IPC分类号： H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号： H01L29/66545 , H01L21/823418 , H01L21/823468 , H01L27/088 , H01L29/0673 , H01L29/0847 , H01L29/42392 , H01L29/66439 , H01L29/66553 , H01L29/775 , H01L29/78696
摘要： A device includes: a stack of semiconductor channels; a gate structure wrapping around the semiconductor channels; a source/drain region abutting the semiconductor channels; a source/drain contact on the source/drain region; and a gate spacer between the source/drain contact and the gate structure. The gate spacer includes: a first spacer layer in contact with the gate structure; and a second spacer layer between the first spacer layer and the source/drain contact, the second spacer layer having a first portion on the stack and a second portion on the first portion, the second portion being thinner than the first portion.
-
-
-
-
-
-
-
-
-
搜索结果
2860 条记录 (耗时 0.029 秒)
