公开(公告)号：US20240161837A1

公开(公告)日：2024-05-16

申请号：US18420073

申请日：2024-01-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27

CPC classification number: G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US20240154045A1

公开(公告)日：2024-05-09

申请号：US18549016

申请日：2022-03-03

Applicant: Diamfab ,  Centre National De La Recherche Scientifique ,  Institut Polytechnique de Grenoble ,  Universite de Grenoble Alpes

Inventor： Gauthier Chicot ,  Khaled Driche ,  David Eon ,  Etienne Gheeraert ,  Cédric Masante ,  Julien Pernot

IPC: H01L29/92 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24

CPC classification number: H01L29/92 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24

Abstract: A capacitor comprises a stack of layers made of a semiconductor material having a band gap energy greater than 2.3 eV, the stack of layers comprising: an electrically insulating intermediate layer having a resistivity greater than 10 kohm·cm and comprising n- or p-type deep dopants producing energy levels more than 0.4 eV from the conduction band or the valence band of the semiconductor material, two contact layers having a resistivity less than or equal to 10 kohm·cm and comprising dopants of a type opposite to that of the deep dopants of the intermediate layer, the two contact layers being arranged on either side of the intermediate layer to form two pin junctions.

公开(公告)号：US11910588B2

公开(公告)日：2024-02-20

申请号：US17643411

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I Lai ,  Chun-Heng Wu

IPC: H10B12/00 ,  H01L49/02 ,  H01L29/92

CPC classification number: H10B12/00 ,  H01L28/40 ,  H01L28/92 ,  H01L29/92

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20230290418A9

公开(公告)日：2023-09-14

申请号：US17934965

申请日：2022-09-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  G06F17/16 ,  G06N3/063

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  H01L29/1037 ,  H01L29/0847 ,  H01L29/78633 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L29/40117 ,  G11C16/0416 ,  G11C16/0491 ,  H01L29/66833 ,  H01L29/7926 ,  G11C16/0466 ,  G06F17/16 ,  G06N3/063 ,  H01L27/11565

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US11710696B2

公开(公告)日：2023-07-25

申请号：US17678232

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu ,  Tse-Yao Huang

IPC: H01L23/00 ,  H01L23/525 ,  H01L23/535 ,  H01L21/3215 ,  H01L29/92 ,  H01L21/28 ,  H01L29/40 ,  H01L23/532 ,  H01L29/49

CPC classification number: H01L23/5252 ,  H01L21/28158 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/401 ,  H01L29/92 ,  H01L23/53271 ,  H01L29/495

Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device including a substrate, a bottom conductive layer positioned in the substrate, a first gate structure including a first gate dielectric layer positioned on the bottom conductive layer, a first work function layer positioned on the first gate dielectric layer, and a first filler layer positioned on the first work function layer, a second gate structure including a second gate dielectric layer positioned on the bottom conductive layer and spaced apart from the first gate dielectric layer, a second work function layer positioned on the second gate dielectric layer, and a second filler layer positioned on the second work function layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first gate structure and the second gate structure.

公开(公告)号：US20220262941A1

公开(公告)日：2022-08-18

申请号：US17621852

申请日：2020-06-24

Applicant: POWER INTEGRATIONS, INC.

Inventor： KUO-CHANG YANG ,  SORIN GEORGESCU ,  ALEXEY KUDYMOV ,  KAMAL VARADARAJAN

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L27/06 ,  H01L29/92

Abstract: Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

公开(公告)号：US11315645B2

公开(公告)日：2022-04-26

申请号：US16820209

申请日：2020-03-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C11/56 ,  H01L29/10 ,  G11C16/04 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as 3-dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

公开(公告)号：US20220085601A1

公开(公告)日：2022-03-17

申请号：US17019746

申请日：2020-09-14

Applicant: Infineon Technologies AG

Inventor： Dethard PETERS ,  Thomas BASLER ,  Paul SOCHOR

IPC: H02H9/04 ,  H01L27/06 ,  H01L49/02 ,  H01L29/92 ,  H01L29/16 ,  H01L29/20 ,  H01L29/808 ,  H01L29/78

Abstract: An apparatus includes a unipolar power transistor and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate. The capacitor has a p-n junction. The RC snubber has a resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

公开(公告)号：US20200243692A1

公开(公告)日：2020-07-30

申请号：US16294944

申请日：2019-03-07

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Liang Chen

IPC: H01L29/92 ,  H01L49/02 ,  H01L29/06

Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

公开(公告)号：US20200227123A1

公开(公告)日：2020-07-16

申请号：US16744067

申请日：2020-01-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Sayeef Salahuddin ,  Robert D. Normal ,  Eli Harari

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792

Abstract: NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.