公开(公告)号：US06822254B1

公开(公告)日：2004-11-23

申请号：US10407516

申请日：2003-04-04

Applicant: Michael L. Lovejoy

Inventor： Michael L. Lovejoy

IPC: H01L2906

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.

Abstract translation: 公开了集成在集成电路中的非易失性存储单元。 非易失性存储单元包括存取晶体管; 耦合到所述存取晶体管的浮栅晶体管; 形成在所述存取晶体管的源极和所述第二晶体管的栅极之间的隧穿电容器; 以及耦合电容器，其具有与所述浮栅晶体管的栅极相关联的第一板，所述第一板被形成为使所述浮栅晶体管的栅极 - 源极电容最小化。 还创建了一个窗口来减小隧道电容器的电容和浮栅晶体管的栅极到源极电容。 还公开了制造该非易失性存储单元的方法。

公开(公告)号：US06818914B2

公开(公告)日：2004-11-16

申请号：US09994731

申请日：2001-11-28

Applicant: Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

Inventor： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC: H01L2906

CPC classification number: H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

Abstract translation: 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

公开(公告)号：US06815727B2

公开(公告)日：2004-11-09

申请号：US10601755

申请日：2003-06-24

Applicant: Takahisa Kurahashi ,  Tetsurou Murakami ,  Shouichi Ohyama ,  Hiroshi Nakatsu

Inventor： Takahisa Kurahashi ,  Tetsurou Murakami ,  Shouichi Ohyama ,  Hiroshi Nakatsu

IPC: H01L2906

CPC classification number: H01L33/105

Abstract: A resonant cavity type light emitting diode has a first DBR made of n-type AlAs or Al0.5Ga0.5As, a quantum well active layer, a second DBR made of p-type (Al0.2Ga0.6)0.5In0.5P or Al0.5In0.5P, and an n-type current constriction layer on an n-type GaAs substrate. The first DBR and the second DBR form a resonator. The quantum well active layer is formed in a position of an antinode of a standing wave inside the resonator. Between the second DBR and the current constriction layer, there is provided a p-type GaP etching protection layer that has a value obtained by dividing resistivity by thickness being 1×103 &OHgr; or more. Since a current in a current flow pass formed in the current constriction layer hardly diffuses to the outside of the current flow pass, there is generated few region with low current density that causes deterioration of responsespeed in a quantum well layer. Thus, the light emitting diode has an excellent high-speed response.

Abstract translation: 谐振腔型发光二极管具有由n型AlAs或Al0.5Ga0.5As制成的第一DBR，量子阱活性层，由p型（Al 0.2 Ga 0.6）0.5 In 0.5 P制成的第二DBR或 Al 0.5 In 0.5 P，n型GaAs衬底上的n型电流收缩层。 第一DBR和第二DBR形成谐振器。 量子阱有源层形成在谐振器内的驻波的波腹的位置。 在第二DBR和电流收缩层之间，提供了一种p型GaP蚀刻保护层，其具有通过将电阻率除以1×10 -3Ω或更大的厚度获得的值。 由于形成在电流收缩层中的电流流动中的电流几乎不扩散到电流流通的外部，所以产生的电流密度低的区域导致量子阱层中的响应速度降低。 因此，发光二极管具有优异的高速响应。

公开(公告)号：US06803598B1

公开(公告)日：2004-10-12

申请号：US09565455

申请日：2000-05-05

Applicant: Paul R. Berger ,  Phillip E. Thompson ,  Roger Lake ,  Karl Hobart ,  Sean L. Rommel

Inventor： Paul R. Berger ,  Phillip E. Thompson ,  Roger Lake ,  Karl Hobart ,  Sean L. Rommel

IPC: H01L2906

CPC classification number: B82Y10/00 ,  H01L29/66151 ,  H01L29/882 ,  Y10S438/979 ,  Y10S438/983

Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.

Abstract translation: 与Si基工艺（例如但不限于CMOS和SiGe HBT制造）兼容的带间隧道二极管。 公开了带间隧道二极管（i）具有围绕隧道势垒的间隔层; （ii）具有与喷射器之一相邻但不一定接触的量子阱，以及（iii）与底部喷射器相邻但不一定与底部喷射器相邻的第一量子阱以及相邻的第二量子阱 但不一定与顶部喷射器接触。 工艺参数包括用于隧道二极管的生长，沉积或转换的温度过程以及随后的热循环，以改进器件基准，例如峰值电流密度和峰谷电流比。

公开(公告)号：US06784450B2

公开(公告)日：2004-08-31

申请号：US10200900

申请日：2002-07-22

Applicant: Noren Pan ,  Byung-Kwon Han

Inventor： Noren Pan ,  Byung-Kwon Han

IPC: H01L2906

CPC classification number: H01L29/66318 ,  H01L29/1004 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor is provided having an improved current gain cutoff frequency. The heterojunction bipolar transistor includes a graded base layer formed from antimony. The graded base allows the heterojunction bipolar transistor to establish a quasi-electric field to yield an improved cutoff frequency.

Abstract translation: 提供具有改善的电流增益截止频率的异质结双极晶体管。 异质结双极晶体管包括由锑形成的分级基底层。 分级基极允许异质结双极晶体管建立准电场以产生改善的截止频率。

公开(公告)号：US06777706B1

公开(公告)日：2004-08-17

申请号：US09743692

申请日：2001-03-21

Applicant: Nir Tessler ,  Peter Ho ,  Richard Henry Friend

Inventor： Nir Tessler ,  Peter Ho ,  Richard Henry Friend

IPC: H01L2906

CPC classification number: B82Y30/00 ,  B82Y20/00 ,  G02B1/10 ,  G02B6/1221 ,  G02B2006/12069 ,  G02B2006/12104 ,  H01L51/5012 ,  H01L51/5262 ,  H01L51/5265 ,  H01L2251/5369 ,  H01S3/168 ,  H01S5/36

Abstract: An optical device having a layer comprising an organic material that includes a substantially uniform dispersion of light transmissive nanoparticles.

Abstract translation: 一种光学器件，其具有包含有机材料的层，该有机材料包括基本均匀的透光纳米粒子的分散体。

公开(公告)号：US06774389B2

公开(公告)日：2004-08-10

申请号：US10290254

申请日：2002-11-08

Applicant: Yoshihiko Hanamaki

Inventor： Yoshihiko Hanamaki

IPC: H01L2906

CPC classification number: H01L33/06 ,  B82Y20/00 ,  H01S5/2231 ,  H01S5/3054 ,  H01S5/3086

Abstract: A semiconductor optical device with improved optical gain and enhanced switching characteristics. The semiconductor optical device includes positive and negative electrodes for providing holes and electrons, respectively. The semiconductor optical device also includes an active layer between the positive and negative electrodes. The active layer includes a multiple quantum well structure having p-type quantum well layers and barrier layers. The quantum well layers are doped with an impurity that diffuses less than zinc so that trapping holes are produced and excessive electrons contributing no light emission are quenched by the trapping holes. The impurity can be beryllium, magnesium, or carbon.

Abstract translation: 具有改善的光学增益和增强的开关特性的半导体光学器件。 半导体光学器件分别包括用于提供空穴和电子的正极和负极。 半导体光学器件还包括在正极和负极之间的有源层。 有源层包括具有p型量子阱层和阻挡层的多量子阱结构。 量子阱层掺杂有杂质，其扩散小于锌，从而产生捕获空穴，并且不产生发光的过量电子被捕获孔骤冷。 杂质可以是铍，镁或碳。

公开(公告)号：US06768131B2

公开(公告)日：2004-07-27

申请号：US10148244

申请日：2002-05-29

Applicant: Mathilde Rüfenacht

Inventor： Mathilde Rüfenacht

IPC: H01L2906

CPC classification number: B82Y20/00 ,  G02F1/01716 ,  G02F2001/213

Abstract: The invention uses the optical nonlinearity of electrically biased exciton polariton in a strong coupling regime or exciton polariton in a strong coupling regime with spatially separated electron and hole pairs. The method comprises providing a signal light (1300) to an exciton polariton system in a strong coupling regime and excitons with spatially separated electron and hole pairs, providing a control light (1302) to the exciton polariton system and removing the control light (1302). Various applications are available, including optical turnstiles, all-optical switches, all-optical phase retardation, low-power saturable transmitters and mirrors. In addition, the applications may operate at single- or few-photon levels.

Abstract translation: 本发明在具有空间分离的电子和空穴对的强耦合状态下，在强耦合方式或激子极化子中使用电偏置的激子极化子的光学非线性。 该方法包括以强耦合方式向激子极化子系统提供信号光（1300）和在空间上分离的电子和空穴对的激子，向激子极化子系统提供控制光（1302）并去除对照光（1302） 。 提供各种应用，包括光学旋转门，全光开关，全光相位延迟，低功耗可饱和发射器和镜子。 此外，应用可以在单光子或少光子水平操作。

公开(公告)号：US06762483B1

公开(公告)日：2004-07-13

申请号：US10348910

申请日：2003-01-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L2906

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06753546B2

公开(公告)日：2004-06-22

申请号：US10231385

申请日：2002-08-29

Applicant: Alexander Ya. Tzalenchuk ,  Zdravko G. Ivanov ,  Miles F. H. Steininger

Inventor： Alexander Ya. Tzalenchuk ,  Zdravko G. Ivanov ,  Miles F. H. Steininger

IPC: H01L2906

CPC classification number: G06N99/002 ,  B82Y10/00 ,  H01L39/225

Abstract: The present invention comprises a junction between an unconventional superconductor, an intermediate material, and a conventional superconducting material. In some embodiments, the unconventional superconductor has an orthorhombic crystal structure and the supercurrent in the resulting junction flows in the c-axis direction of the orthorhombic crystal. In other embodiments, the supercurrent flows parallel to a direction in the a-b plane. Interface junctions according to embodiments of the present invention may be used in superconducting low inductance qubits (SLIQs) and in permanent readout superconducting qubits (PRSQs), can form the basis of quantum registers, and can permit parity keys or other devices made from conventional superconducting material to be attached to qubits made from unconventional superconducting material or vice versa. Coherent tunnel junctions according to embodiments of the present invention may be used to form parity keys or to coherently couple two regions of a superconducting material.

Abstract translation: 本发明包括非常规超导体，中间材料和常规超导材料之间的接合部。 在一些实施例中，非常规超导体具有正交晶体结构，并且所得结中的超电流在正交晶体的c轴方向上流动。 在其它实施例中，超电流平行于a-b平面中的方向流动。 根据本发明的实施例的接口结可以用于超导低电平量子位（SLIQ）和永久读出超导量子位（PRSQ）中，可以形成量子寄存器的基础，并且可以允许奇偶校验键或由常规超导制成的其他器件 要连接到由非常规超导材料制成的量子位的材料，反之亦然。 根据本发明的实施例的相干隧道结可用于形成奇偶校验键或相干地耦合超导材料的两个区域。