Schottky diode
    4.
    发明授权

    公开(公告)号:US11637210B2

    公开(公告)日:2023-04-25

    申请号:US16771400

    申请日:2018-12-11

    Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

    OFETs having multilayer organic semiconductor with high on/off ratio

    公开(公告)号:US11631818B2

    公开(公告)日:2023-04-18

    申请号:US17098493

    申请日:2020-11-16

    Abstract: An organic field effect transistor includes a channel structure having a photoalignment layer and an organic semiconductor layer disposed directly over the photoalignment layer, where a charge carrier mobility varies along a thickness direction of the channel structure. The channel structure may define an active area between a source and a drain of the transistor and may include alternating layers of at least two photoalignment layers and at least two organic semiconductor layers. Each photoalignment layer is configured to influence an orientation of molecules within an overlying organic semiconductor layer and hence impact the mobility of charge carriers within the device active area while also advantageously decreasing the OFF current of the device.

    Memory cell based on self-assembled monolayer polaron

    公开(公告)号:US20230041969A1

    公开(公告)日:2023-02-09

    申请号:US17394515

    申请日:2021-08-05

    Abstract: A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

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