公开(公告)号：US06807242B1

公开(公告)日：2004-10-19

申请号：US09679079

申请日：2000-10-05

申请人： Masahiko Mutoh

发明人： Masahiko Mutoh

IPC分类号： H03D100

CPC分类号： H04B1/709 ,  H04B1/707 ,  H04L27/2278 ,  H04L2027/0046 ,  H04L2027/0065 ,  H04L2027/0083

摘要： To provide an apparatus for calculation of correlation that can take in correlation even when a frequency error is relatively large. With a 0-th degree correlator for taking, to output, a correlation between a reference signal and a measurement signal, an n-th degree correlator including an ej&ohgr;t multiplier for calculating a frequency component addition signal having a frequency component added to the reference signal, and a correlation calculator for taking, to output, a correlation between the frequency component addition signal and the measurement signal, and an adder for adding an output of the 0-th degree correlator and an output of the n-th degree correlator, it is achieved that the output of the 0-th degree correlator and the output of the n-th degree correlator added at the adder do not have an increased noise/correlation value ratio, even when a frequency error is large. Accordingly, a correlation can be taken even with an increased frequency error.

摘要翻译： 提供一种用于计算相关性的装置，即使在频率误差相对较大时也可以进行相关。 对于用于获取，输出参考信号和测量信号之间的相关性的第0度相关器，包括用于计算频率分量添加到频率分量的频率分量相加信号的第n次相关器，其包括e 参考信号和相关计算器，用于输出频率分量相加信号和测量信号之间的相关性，以及用于将第0次相关器的输出和第n次相关器的输出相加的加法器 相关器，即使在频率误差大的情况下，也能够实现在加法器中添加的第0次相关器的输出和第n次相关器的输出不具有增加的噪声/相关值比。 因此，即使增加的频率误差也可以进行相关。

公开(公告)号：US06803815B1

公开(公告)日：2004-10-12

申请号：US10252578

申请日：2002-09-24

申请人： Osamu Nishikido

发明人： Osamu Nishikido

IPC分类号： H03D100

CPC分类号： H03D1/2281

摘要： A first automatic phase control (APC) detection circuit generates an APC detection signal having normal polarity from an amplitude modulation signal and APC detection reference signal. A second APC detection circuit generates an APC detection signal having reverse polarity from the amplitude modulation signal and the APC detection reference signal. A switch selects the APC detection signal having normal polarity in case of normal modulation and selects the APC detection signal having reverse polarity in case of overmodulation.

摘要翻译： 第一自动相位控制（APC）检测电路从幅度调制信号和APC检测参考信号产生具有正常极性的APC检测信号。 第二APC检测电路从幅度调制信号和APC检测参考信号产生具有相反极性的APC检测信号。 在正常调制的情况下，开关选择具有正常极性的APC检测信号，并且在过调制的情况下选择具有相反极性的APC检测信号。

公开(公告)号：US06788749B2

公开(公告)日：2004-09-07

申请号：US09747112

申请日：2000-12-21

申请人： Johannes Otto Voorman ,  Johannes Wilhelmus Maria Bergmans ,  Ho Wai Wong-Lam

发明人： Johannes Otto Voorman ,  Johannes Wilhelmus Maria Bergmans ,  Ho Wai Wong-Lam

IPC分类号： H03D100

CPC分类号： H04L25/03057 ,  H04L7/0062

摘要： A receiver for restoring a data signal from a data input signal, comprises a data detector and a control signal generator coupled to the data detector for controlling one or more loops in the data detector, such as an automatic gain control, an equalizer adaptation and/or a timing recovery loop. The receiver also comprises erasure means for generating an instantaneous erasure information signal in case the data input signal to be restored falls within an erasure zone, which erasure means are coupled to the control signal generator for essentially instantaneous use of the instantaneous erasure information for accurate loop control. Preferably the respective control signals are kept constant in time during periods of erasure.

摘要翻译： 用于从数据输入信号恢复数据信号的接收机包括数据检测器和耦合到数据检测器的控制信号发生器，用于控制数据检测器中的一个或多个环路，诸如自动增益控制，均衡器适配和/ 或定时恢复循环。 接收机还包括擦除装置，用于在要恢复的数据输入信号落在擦除区内的情况下产生瞬时擦除信息信号，该擦除装置耦合到控制信号发生器，用于基本上即时使用瞬时擦除信息以进行精确的环路 控制。 优选地，各个控制信号在擦除期间在时间上保持恒定。

公开(公告)号：US06784730B2

公开(公告)日：2004-08-31

申请号：US10442736

申请日：2003-05-21

申请人： Shigeru Arisawa

发明人： Shigeru Arisawa

IPC分类号： H03D100

CPC分类号： G06K7/0008 ,  G06K19/0723 ,  H03C1/08 ,  H03C1/14 ,  H03C1/36 ,  H03F3/72 ,  H03F2200/327 ,  H03F2203/7215 ,  H03K7/02 ,  H04L27/04 ,  H04L27/06

摘要： In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal, a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal, gate means for gating at least the second output signal, calculation means for adding, or subtracting the first output signal and the second output signal; and control means for controlling the operation of the gate means in response to a logic level of input data.

摘要翻译： 在非接触IC卡系统中，以IC形式制造的调制电路以高功率效率工作。 解调装置被配置为包括：第一信号输出装置，用于输出相对于输入信号具有预定相位的第一输出信号;第二信号输出装置，用于输出具有预定相位的第二输出信号，该第二输出信号具有相对于 至少选择第二输出信号的门装置，用于相加或减去第一输出信号和第二输出信号的计算装置; 以及用于响应于输入数据的逻辑电平来控制门装置的操作的控制装置。

公开(公告)号：US06771716B1

公开(公告)日：2004-08-03

申请号：US09229127

申请日：1999-01-12

申请人： Jean-Marie Gaultier

发明人： Jean-Marie Gaultier

IPC分类号： H03D100

CPC分类号： H04L25/45 ,  G06F13/4291

摘要： A method of communication between a master unit and a slave unit is of the type including the transmission of messages comprising a useful information word, as well as one or more service bits. The messages include two bits to encode the end-of-transmission information. The value of these bits provides information on the nature of the useful information transmitted to thereby improve the integrity of the communications.

摘要翻译： 主单元和从单元之间的通信方式是包括传输包括有用信息字的消息以及一个或多个服务位的类型。 消息包括两个比特来编码传输结束信息。 这些位的值提供关于传输的有用信息的性质的信息，从而提高通信的完整性。

公开(公告)号：US06760390B1

公开(公告)日：2004-07-06

申请号：US09696784

申请日：2000-10-25

申请人： Vipul Anil Desai ,  Brian Keith Classon ,  Thomas Keith Blankenship

发明人： Vipul Anil Desai ,  Brian Keith Classon ,  Thomas Keith Blankenship

IPC分类号： H03D100

CPC分类号： H04L1/0055 ,  H04L25/067 ,  H04L27/22 ,  H04L27/38

摘要： The log-add kernel operation is represented as a summation of an average and a correction factor composed of a constant and a term based on a difference between the input arguments. In a described embodiment, the correction factor is approximated using the reduction of the correction factor into a Taylor series expansion, which may be defined around the difference between the input arguments as approximately zero. The approach may be further optimized to provide the Taylor series expansion as being modified to compute the correction factor with simple additions, multiplications, and shift operations. If the input arguments are close to each other, the new computed representation may be used, and if the arguments are further apart, the max operation is used. The log-add kernel operation also may be extended to more than two arguments, for application, for example, in the kernel operation of the generalized Viterbi decoder with a branch fan-in greater than 2. Additionally, a method of computing bit soft values for symbols of a higher-order modulation using log-add operations is disclosed, where each log-add is provided as an approximation including a primary term and a parameterized correction factor. Performance close to the optimal soft value generation is achieved at roughly the same complexity as the dual-min algorithm.

摘要翻译： 日志添加内核操作被表示为基于输入参数之间的差异的由常数和项组成的平均值和校正因子的总和。 在所描述的实施例中，使用将校正因子减少到泰勒级数展开来近似校正因子，其可以围绕输入参数之间的差定义为大约零。 可以进一步优化该方法以提供泰勒级数展开，以便通过简单的添加，乘法和移位操作来修改以计算校正因子。 如果输入参数彼此靠近，则可以使用新的计算表示，如果参数进一步分开，则使用最大运算。 日志添加内核操作也可以扩展到两个以上的参数，例如在分支扇入大于2的广义维特比解码器的内核操作中的应用。另外，一种计算位软值的方法 公开了使用日志加法运算的高阶调制的符号，其中每个逻辑加法被提供为包括主项和参数化校正因子的近似。 接近最佳软值生成的性能实现了与双精度算法大致相同的复杂度。

公开(公告)号：US06754291B1

公开(公告)日：2004-06-22

申请号：US09523844

申请日：2000-03-13

申请人： Kazuhiro Okanoue ,  Takeshi Yamamoto

发明人： Kazuhiro Okanoue ,  Takeshi Yamamoto

IPC分类号： H03D100

CPC分类号： H04L25/067

摘要： A method of outputting a demodulation result for soft-decision decoding is provided, which is comprised of the steps of: (a) detecting a channel distortion of a received signal generated in a communication channel using a training signal contained in the received signal and a reference training signal, outputting a channel distortion data: (b) generating a distortion-based reliability data from the channel distortion data; (c) compensating the received signal using the channel distortion data, generating a compensated, received signal; (d) demodulating the compensated, received signal and deciding the received signal thus demodulated using a soft decision technique, outputting a decision result; and (e) outputting a demodulation result using the decision result and the distortion-based reliability data.

摘要翻译： 提供一种输出用于软判决解码的解调结果的方法，其包括以下步骤：（a）使用接收信号中包含的训练信号检测在通信信道中产生的接收信号的信道失真，以及 参考训练信号，输出信道失真数据：（b）从信道失真数据生成基于失真的可靠性数据; （c）使用信道失真数据补偿接收信号，产生经补偿的接收信号; （d）解调补偿的接收信号，并使用软判决技术确定所解调的接收信号，输出判定结果; 和（e）使用判定结果和基于失真的可靠性数据输出解调结果。

公开(公告)号：US06714607B2

公开(公告)日：2004-03-30

申请号：US10037300

申请日：2001-12-20

申请人： Richard A. Kobylinski ,  David Randall Wolter

发明人： Richard A. Kobylinski ,  David Randall Wolter

IPC分类号： H03D100

CPC分类号： H04L25/0208 ,  H04B1/1081 ,  H04L25/0204 ,  H04L25/0212 ,  H04L25/0224 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03331 ,  H04L27/2017 ,  H04L2025/03407

摘要： A desired signal and at least one interfering signal are joint demodulated with a Viterbi equalizer having an adaptive total number of states. The total number of states is based on channel impulse response (CIR) coefficients associated with the desired signal and the at least one interfering signal.

摘要翻译： 期望的信号和至少一个干扰信号与具有自适应总数状态的维特比均衡器联合解调。 总状态数是基于与期望信号和至少一个干扰信号相关联的信道脉冲响应（CIR）系数。

公开(公告)号：US06697443B1

公开(公告)日：2004-02-24

申请号：US09679925

申请日：2000-10-05

申请人： Min-Goo Kim ,  Beong-Jo Kim ,  Young-Hwan Lee

发明人： Min-Goo Kim ,  Beong-Jo Kim ,  Young-Hwan Lee

IPC分类号： H03D100

CPC分类号： H04L1/0054 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4146 ,  H03M13/4184 ,  H03M13/6583 ,  H04L1/0052

摘要： There is provided a decoder and a decoding method for decoding data modulated with a recursive systematic convolutional code (RSC) in a mobile communication system. In the decoder, a branch metric calculating circuit (BMC) calculates branch metrics (BMs) associated with a plurality of input symbols. An add-compare-select circuit (ACS) receives the BMs and previous path metrics (PMs) and generates an plurality of path selectors and LLR (Log Likelihood Ratio) data including the plurality of path selectors and reliability information at a first time instant. A maximum likelihood (ML) state searcher has a plurality of cells in an array with rows and columns, connected to one another according to an encoder trellis, cells in each row having a process time, Ds, for outputting the same value of the cells in the last column as an ML state value representing an ML path in response to the path selectors. A delay delays the LLR data received from the ACS by the time Ds. An LLR update circuit has a plurality of processing elements (PEs) in an array with rows and columns, connected according to the encoder trellis, PEs in each row having a process time, DL, for generating updated LLR values from the PEs at a time instant (first time instant−approximately DS+DL) in response to the delayed LLR data received from the delay. A selector selects one of the updated LLR values based on the ML state value.

摘要翻译： 提供了一种用于在移动通信系统中对用循环系统卷积码（RSC）进行调制的数据进行解码的解码器和解码方法。 在解码器中，分支度量计算电路（BMC）计算与多个输入符号相关联的分支度量（BM）。 加法比较选择电路（ACS）接收BM和以前的路径度量（PM），并且在第一时刻产生包括多个路径选择器和可靠性信息的多个路径选择器和LLR（对数似然比）数据。 最大似然（ML）状态搜索器具有根据编码器网格彼此连接的具有行和列的阵列中的多个单元，每行中的单元具有处理时间Ds，用于输出单元格的相同值 在最后一列中作为响应于路径选择器的ML路径的ML状态值。 延迟延迟从ACS接收的LLR数据Ds。 LLR更新电路具有多个处理元件（PE），其具有根据编码器网格连接的具有行和列的阵列，每行中的PE具有处理时间DL，用于一次从PE生成更新的LLR值 响应于从延迟接收的延迟的LLR数据，即时（第一时刻 - 近似DS + DL）。 选择器根据ML状态值选择一个更新的LLR值。

公开(公告)号：US06687315B2

公开(公告)日：2004-02-03

申请号：US09995011

申请日：2001-11-27

申请人： Peter A Keevill ,  Dawood Alam ,  John M. Nolan ,  Matthew J Collins ,  Thomas Foxcroft ,  David H. Davies ,  Jonathan Parker

发明人： Peter A Keevill ,  Dawood Alam ,  John M. Nolan ,  Matthew J Collins ,  Thomas Foxcroft ,  David H. Davies ,  Jonathan Parker

IPC分类号： H03D100

CPC分类号： H04L27/2678 ,  H04L27/265 ,  H04L27/2662

摘要： The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

摘要翻译： 本发明提供了通过正交频分复用传输的用于多载波信号的数字接收机的单芯片实现。 提供改进的信道估计和校正电路。 接收机具有高精度的采样率控制和频率控制电路。 使用包括小伽罗瓦域乘法器的布置的最小资源来实现tps数据载体的BCH解码。 改进的FFT窗口同步电路耦合到重采样电路，用于定位与信号的有效帧一起发送的保护间隔的边界。 实时流水线FFT处理器与FFT窗口同步电路可操作地相关联，并以较少的存储器要求进行操作。