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公开(公告)号：US12224714B1
公开(公告)日：2025-02-11
申请号：US17322517
申请日：2021-05-17
Applicant: AmpliTech, Inc.
Inventor： Fawad Maqbool
Abstract: The present disclosure is directed to apparatus and method that extends a useful operation range of an amplifier circuit. Here a low noise amplifier may be attached to a cold end of a cooler or chiller, such as a “Stirling” cryocooler after which a chamber that encloses the cold end of the cooler and the amplifier may be assembled. Gas included in the chamber may be removed by attaching an input to a vacuum pump to a portion of the chamber. After the chamber is sealed such that a low pressure in the chamber can be maintained, the cooler may be turned on in order to chill the amplifier to temperatures that reduce noise generated internally to the amplifier or to reduce amounts of return loss associated with the amplifier. The use of a Stirling cryocooler allows for the amplifier to be cooled to very low or cryogenic temperatures.
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公开(公告)号：US12191816B2
公开(公告)日：2025-01-07
申请号：US17643675
申请日：2021-12-10
Applicant: Qorvo US, Inc.
Inventor： Marcus Granger-Jones
Abstract: A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.
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公开(公告)号：US12184244B2
公开(公告)日：2024-12-31
申请号：US17369879
申请日：2021-07-07
Applicant: The Regents of the University of California
Inventor： Hadi Bameri , Omeed Momeni
Abstract: A power amplifier (amp) is disclosed. This power amp can include a first transistor configured in the common source (CS) amplification mode, wherein the gate terminal of the first transistor is used as the input port of the power amp; and a second transistor configured in the common gate (CG) amplification mode, wherein the drain terminal of the second transistor is used as the output port of the power amp. The power amp also includes a first inductive component coupled between the drain terminal of the first transistor and the ground to increase the impedance between the drain terminal of the first transistor and the ground, thereby increasing an output power at the output port. The power amp additionally includes a second inductive component coupled between the drain terminal of the first transistor and the source terminal of the second transistor to increase the conductance in the output admittance at the output port, thereby further increasing the output power at the output port.
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公开(公告)号：US20240405724A1
公开(公告)日：2024-12-05
申请号：US18656926
申请日：2024-05-07
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US20240396503A1
公开(公告)日：2024-11-28
申请号：US18790254
申请日：2024-07-31
Applicant: pSemi Corporation
Inventor： Miles SANNER , Emre AYRANCI , Parvez DARUWALLA
Abstract: Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.
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Patent Agency Ranking
公开(公告)号：US20240348211A1
公开(公告)日：2024-10-17
申请号：US18624973
申请日：2024-04-02
Applicant: pSemi Corporation
Inventor： Jonathan James Klaren , David Kovac , Eric S. Shapiro , Christopher C. Murphy , Robert Mark Englekirk , Keith Bargroff , Tero Tapio Ranta
CPC classification number: H03F1/223 , H03F1/301 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/165 , H03F2200/18 , H03F2200/21 , H03F2200/222 , H03F2200/225 , H03F2200/243 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/42 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/498 , H03F2200/555 , H03F2200/61 , H03F2200/78
Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
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7.发明授权公开(公告)号：US12113486B2
公开(公告)日：2024-10-08
申请号：US17378564
申请日：2021-07-16
Applicant: The Boeing Company
Inventor： Chris M. Thomas , Brian K. Kormanyos
CPC classification number: H03F1/223 , H03F1/0222 , H03F3/195 , H03F3/245 , H03F2200/318 , H03F2200/451
Abstract: An amplifier with stacked transconducting cells in parallel and/or cascade “current mode” combining is disclosed herein. In one or more embodiments, a method for operation of a high-voltage signal amplifier comprises inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (IRF_IN), and an RF input signal (RFIN). The method further comprises outputting, by each of the transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (IRF_OUT). In one or more embodiments, the transconducting cells are connected together in cascode for the DC supply current (Idc), are connected together in parallel (or in cascade) for the RF input signal (RFIN), and are connected together in parallel (or in cascade) for the AC RF output currents (IRF_OUT).
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公开(公告)号：US20240297625A1
公开(公告)日：2024-09-05
申请号：US18177164
申请日：2023-03-02
Applicant: QUALCOMM INCORPORATED
Inventor： Sadia AFROZ , Conor DONOVAN
CPC classification number: H03F3/45192 , H03F1/223 , H03F1/26 , H03F1/565 , H03F2200/451
Abstract: A transimpedance-based baseband filter (BBF) including a two-stage operational transconductance amplifier (OTA) having a first stage based on a folded cascode topology, the first stage electrically coupled to a second stage, the second stage having a class AB topology, the first stage having an N-type and P-type transistor pair located between a P-type transistor and an N-type transistor, the N-type and P-type transistor pair configured to provide bias signals to push-pull transistors in the second stage.
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公开(公告)号：US12068724B2
公开(公告)日：2024-08-20
申请号：US17403595
申请日：2021-08-16
Applicant: QUALCOMM Incorporated
Inventor： Gary Lee Brown, Jr. , Chirag Dipak Patel
CPC classification number: H03F3/195 , H03F1/223 , H03H7/20 , H03H7/38 , H03F2200/204
Abstract: Aspects of the disclosure relate to a radio frequency phase shifter. An example includes an amplification stage to produce an amplified voltage, the amplification stage having a first amplifier with a first input coupled to a first output of a hybrid coupler and a second amplifier with a complementary second input coupled to a complementary second output of the hybrid coupler. A vector modulation stage coupled to the amplification stage receives the amplified voltage and produces a modulated vector, the vector modulation stage has an in-phase section and a quadrature section to control the phase of the modulated vector in response to a phase control signal. A varactor coupled across the first input and the second input of the amplification stage adjusts the capacitance between the first input and the second input in response to a capacitance control signal.
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10.发明公开公开(公告)号：US20240223144A1
公开(公告)日：2024-07-04
申请号：US18527346
申请日：2023-12-03
Applicant: LITE-ON SINGAPORE PTE. LTD.
Inventor： Yoshio Nishida
CPC classification number: H03F3/45748 , H03F1/223 , H03F3/45237 , H03F2203/45212
Abstract: A two-stage common-mode feedback (CMFB) circuit and a fully differential operational amplifier are provided. The two-stage CMFB circuit includes a first CMFB circuit and a second CMFB circuit. The first CMFB circuit includes a first CMFB component that receives a first differential pair of output signals of the first amplifier and a first reference signal. The first CMFB component generates a first control signal to regulate a first common-mode voltage of the first amplifier to a first reference voltage of the first reference signal. The second CMFB circuit includes a second CMFB component that receives a second differential pair of output signals of the second amplifier and a second reference signal. The second CMFB component generates a second control signal according to a second reference signal, so as to regulate a second common-mode voltage of the second amplifier to a second reference voltage of the second reference signal.
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