公开(公告)号：US11705892B2

公开(公告)日：2023-07-18

申请号：US17674600

申请日：2022-02-17

申请人： Skyworks Solutions, Inc.

发明人： Péter Onódy ,  András V. Horváth

IPC分类号： H03K5/125 ,  H03K5/1252 ,  H03H11/06 ,  H03H11/26 ,  H03K3/012 ,  H03K17/687 ,  H03K19/20

CPC分类号： H03K3/012 ,  H03K17/6872 ,  H03K17/6874 ,  H03K19/20

摘要： A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

公开(公告)号：US20230223927A1

公开(公告)日：2023-07-13

申请号：US18096171

申请日：2023-01-12

申请人： Kumu Networks, Inc.

发明人： Wilhelm Steffen Hahn

IPC分类号： H03H9/54 ,  H03H11/16 ,  H03H11/26 ,  H03H11/24

CPC分类号： H03H9/54 ,  H03H11/16 ,  H03H11/26 ,  H03H11/24 ,  H03H9/02102

摘要： A system for filter enhancement, preferably including one or more analog taps and a controller, and optionally including one or more couplers. The system is preferably configured to integrate with a filter, such as a passband filter or other frequency-based filter. The system can be configured to integrate with an RF communication system, an RF front end, or any other suitable RF circuitry. A method for filter enhancement, preferably including configuring one or more analog taps, and optionally including calibrating a system for filter enhancement and/or receiving temperature information.

公开(公告)号：US10992285B2

公开(公告)日：2021-04-27

申请号：US16655427

申请日：2019-10-17

申请人： FUJITSU LIMITED

发明人： Shoichi Shiba ,  Toshiaki Nagai

IPC分类号： H01P1/207 ,  H01P1/208 ,  H03H11/26 ,  H01P7/06 ,  H01P1/209

摘要： A group delay compensation filter includes: a waveguide that has a first slot and that is configured to transmit a signal; and a first dielectric resonator that includes: a first dielectric, a first metal layer formed over a surface of the first dielectric, and a first opening provided in the first metal layer, wherein the first dielectric resonator is in contact with the waveguide with the first opening coupled to the first slot, and wherein the first dielectric resonator is configured to compensate group delay in a first frequency band of the signal.

公开(公告)号：US20190296718A1

公开(公告)日：2019-09-26

申请号：US16372194

申请日：2019-04-01

申请人： pSemi Corporation

发明人： John Birkbeck ,  Vikas Sharma ,  Kashish Pal ,  Mark James O'Leary

IPC分类号： H03H11/20 ,  H03H11/26 ,  H03H17/00 ,  H03H17/08

摘要： A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

公开(公告)号：US10313165B2

公开(公告)日：2019-06-04

申请号：US15453774

申请日：2017-03-08

申请人： Credo Technology Group Limited

发明人： Lawrence Chi Fung Cheng ,  Haihui Luo

IPC分类号： H03F3/21 ,  H03F3/193 ,  H04L25/03 ,  H04L27/01 ,  H03F3/45 ,  H03G5/28 ,  H03H11/26 ,  H03H15/02

摘要： High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

公开(公告)号：US09991874B1

公开(公告)日：2018-06-05

申请号：US15341829

申请日：2016-11-02

申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION

发明人： Timothy R. LaRocca ,  Denpol Kultran

IPC分类号： H03H11/04 ,  H03H11/26 ,  H03H11/32

CPC分类号： H03H15/02 ,  H03H2015/007

摘要： A tunable analog noise-cancelling transversal reconfigurable filter for filtering an RF signal. The filter includes a noise-cancelling balun responsive to the RF signal and providing gain and noise suppression, and a time delay network responsive to the signal from the balun. The time delay network includes a single continuous three-dimensional air coaxial line where a separate tap is provided between sections of the line. The filter also includes a multiplication and summing network having a plurality of multiplication stages, where each stage is fed by a voltage signal from at least one of the taps, and each stage includes a multiplication amplifier that amplifies the voltage signal. A tuning element provides a multiplication coefficient to the amplified signal. Each amplified signal in each stage is added on an output line, where the multiplication and summing network operates under Millman's Theorem.

公开(公告)号：US20180059706A1

公开(公告)日：2018-03-01

申请号：US15675109

申请日：2017-08-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung Ho KIM ,  Junseok KIM ,  Yunjae SUH

IPC分类号： G05F3/20 ,  G05F3/24 ,  G05F3/26 ,  H02M1/08 ,  G05F1/46 ,  H03H11/26 ,  H03K5/133 ,  H02M7/217 ,  H03L7/081

摘要： A current control circuit and a bias generator including the current control circuit are provided. The bias generator may include a current mirror circuit configured to generate one of a first current and a second current based on a reference current; a switch circuit configured to transfer one of the first current and the second current to a variable resistor; an operational amplifier including a first input node connected to the switch circuit, a second input node that receives a reference voltage, and an output node that outputs a bias voltage; and the variable resistor connected between the first input node and the output node of the operational amplifier. By switching operation of the switch circuit, a direction in which the first current flows in the variable resistor may be different from a direction in which the second current flows in the variable resistor.

公开(公告)号：US09742386B2

公开(公告)日：2017-08-22

申请号：US14969641

申请日：2015-12-15

申请人： Apple Inc.

发明人： Haiming Jin

IPC分类号： H03H11/26 ,  H03K5/15

CPC分类号： H03K5/15 ,  H03K5/1504

摘要： Clock generation circuits including a single and multi-phase clock circuits are disclosed. A clock generation circuit is coupled to receive a first pulse on a first input and a second pulse on a second input. The first pulse may be generated responsive to a rising edge of an input clock signal, while the second pulse may be generated responsive to a falling edge of the input clock signal. Responsive to the first pulse, an output node of the clock generation circuit may be pulled high. Responsive to the second pulse, the output node may be pulled low. During those points in which neither pulse is asserted, a state element in the clock generation circuit may hold the output node to its most recent value. Using delay elements and multiple instances of the clock generation circuit and pulse generation circuits, a multi-phase clock generation circuit may be constructed.

公开(公告)号：US20170230037A1

公开(公告)日：2017-08-10

申请号：US15496924

申请日：2017-04-25

申请人： KISKEYA MICROSYSTEMS LLC

发明人： Marc Péralte Dandin

IPC分类号： H03K5/134 ,  H03K17/74 ,  H01L31/107 ,  H01L31/02 ,  H03H11/26

CPC分类号： H03K5/134 ,  G01J1/44 ,  G01J2001/442 ,  G01J2001/4466 ,  H01L31/02027 ,  H01L31/107 ,  H03H11/265 ,  H03K5/133 ,  H03K5/1534 ,  H03K17/74 ,  H03K2005/00026 ,  H03K2005/00156

摘要： A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

公开(公告)号：US09712145B2

公开(公告)日：2017-07-18

申请号：US14939255

申请日：2015-11-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tsung-Ching Huang ,  Chih-Chang Lin ,  Fu-Lung Hsueh

IPC分类号： H03K5/14 ,  H03H11/26 ,  H03K5/133 ,  H03K5/00

CPC分类号： H03K5/14 ,  H03K5/133 ,  H03K2005/00019 ,  H03K2005/00071

摘要： A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.