公开(公告)号：US06812763B1

公开(公告)日：2004-11-02

申请号：US10608303

申请日：2003-06-30

申请人： Hung C. Lin ,  Chiang H. Yeh

发明人： Hung C. Lin ,  Chiang H. Yeh

IPC分类号： H03H1116

CPC分类号： H03H11/16 ,  H03D7/1441 ,  H03D7/165 ,  H03D2200/0033 ,  H03D2200/0043

摘要： When two sine-wave signals in quadrature, the integral of the output is equal to zero. Conversely, when an in-phase signal is inputted as one multiplicand and the output is set to zero, a quadrature signal is derived from the second multiplicand automatically. Any analog multiplier can be used. Examples using differential pair and conductance multiplier have been demonstrated. The multiplier operates over a wideband, and the in phase and quadrature signals can be equalized automatically.

摘要翻译： 当正交两个正弦波信号时，输出的积分等于零。 相反，当同相信号作为一个被乘数输入并且输出被设置为零时，自动地从第二被乘数导出正交信号。 可以使用任何模拟乘法器。 已经证明了使用差分对和电导乘数的例子。 乘法器在宽带上工作，同相和正交信号可以自动相等。

公开(公告)号：US06586983B2

公开(公告)日：2003-07-01

申请号：US10102768

申请日：2002-03-22

申请人： Jun Tsuiki ,  Toshiyuki Shimizu

发明人： Jun Tsuiki ,  Toshiyuki Shimizu

IPC分类号： H03H1116

CPC分类号： H04L7/04 ,  H03L7/00 ,  H04L7/0337

摘要： A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

公开(公告)号：US06580301B2

公开(公告)日：2003-06-17

申请号：US09884376

申请日：2001-06-18

申请人： David Moshe ,  Eyal Gutkind ,  Shmuel Dino ,  Maksim Tozik

发明人： David Moshe ,  Eyal Gutkind ,  Shmuel Dino ,  Maksim Tozik

IPC分类号： H03H1116

CPC分类号： H03L7/0805 ,  G06F1/10 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/159 ,  H03K2005/00286 ,  H03L7/0814

摘要： An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

公开(公告)号：US06452434B1

公开(公告)日：2002-09-17

申请号：US09668381

申请日：2000-09-25

申请人： Kazuyoshi Arimura ,  Tsuyoshi Moribe

发明人： Kazuyoshi Arimura ,  Tsuyoshi Moribe

IPC分类号： H03H1116

CPC分类号： H03H11/18

摘要： A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.

公开(公告)号：US06329858B1

公开(公告)日：2001-12-11

申请号：US09433870

申请日：1999-11-04

申请人： Toshiharu Sobue

发明人： Toshiharu Sobue

IPC分类号： H03H1116

CPC分类号： G06F1/10 ,  G06F5/06 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/02

摘要： A control method and system are used for signal transmission when a data signal is transmitted between two circuits on the basis of a reference clock in a system. The sending side circuit transmits a clock signal together with the data signal to a clock transmission line of the same course with a data transmission line for the data signal by using a sender side reference clock. The receiving side circuit adjusts phases of the clock signal and the data signal at input points of transmission lines respectively so as to be in accordance with a receiver side reference clock. Then the receiving side circuit reads out data from an adjusted data signal by using an adjusted clock obtained by above the aforementioned adjusting step. The adjustment is performed comparing a phase of an adjusted clock with a phase of the receiver side reference clock. The second adjustment involves generating a feedback clock signal including a phase difference between the above signals. And the third one is to adjust phases of the sender side clock signal and the data signal respectively so as to accord with the receiver side reference clock, by using of the above feedback clock.

摘要翻译： 当在系统中基于参考时钟在两个电路之间传输数据信号时，控制方法和系统用于信号传输。 发送侧电路通过使用发送侧参考时钟，将数据信号与时钟信号一起发送到与数据信号的数据传输线相同的时钟传输线。 接收侧电路分别在传输线的输入点处调整时钟信号和数据信号的相位，以便根据接收机侧参考时钟。 然后，接收侧电路通过使用通过上述调整步骤获得的调整时钟从调整数据信号中读出数据。 将调整后的时钟的相位与接收机侧参考时钟的相位进行比较。 第二调整涉及产生包括上述信号之间的相位差的反馈时钟信号。 第三种是通过使用上述反馈时钟来分别调整发送器侧时钟信号和数据信号的相位，使其与接收机侧参考时钟一致。

公开(公告)号：US06307416B1

公开(公告)日：2001-10-23

申请号：US09519541

申请日：2000-03-06

申请人： Patrick Heyne ,  Thoralf Graëtz ,  Dieter Härle

发明人： Patrick Heyne ,  Thoralf Graëtz ,  Dieter Härle

IPC分类号： H03H1116

CPC分类号： H03K5/1515 ,  H03K3/356113

摘要： The integrated circuit has two inputs each supplying one input clock. Two outputs each output one output clock. The first logic levels of the output clock signals at the outputs do not overlap in time.

摘要翻译： 集成电路具有两个输入，每个输入提供一个输入时钟。 两个输出端输出一个输出时钟。 输出端的输出时钟信号的第一个逻辑电平在时间上不重叠。

公开(公告)号：US06822496B2

公开(公告)日：2004-11-23

申请号：US10337047

申请日：2003-01-03

申请人： Takeshi Fukuda

发明人： Takeshi Fukuda

IPC分类号： H03H1116

CPC分类号： H03H7/21 ,  H03K2005/00286

摘要： Disclosed is an integrated circuit device in which a 90-degree phase shifter is implemented. The 90-degree phase shifter includes four input capacitors all having equal capacitance and four output capacitors all having equal capacitance. The input capacitors and the output capacitors are alternately arranged in a loop-shape array in plan view. Eight resistors of the 90-degree phase shifter are arranged inside the annular shape in which the capacitors are arranged.

摘要翻译： 公开了一种其中实现了90度移相器的集成电路器件。 90度移相器包括四个具有相等电容的输入电容和四个具有相等电容的输出电容。 输入电容器和输出电容器在平面图中交替布置成环形阵列。 90度移相器的八个电阻器布置在其中布置有电容器的环形内部。

公开(公告)号：US06768364B2

公开(公告)日：2004-07-27

申请号：US10245823

申请日：2002-09-16

申请人： Sung-ho Wang

发明人： Sung-ho Wang

IPC分类号： H03H1116

CPC分类号： H03B27/00 ,  H03H7/21 ,  H03H2007/0192

摘要： A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

摘要翻译： 正交信号发生器包括多相滤波器，其中四个电阻元件和四个可变电容元件串联交替地形成环路; 以及可变地控制可变电容元件的电容的相位校正器。

公开(公告)号：US06580300B2

公开(公告)日：2003-06-17

申请号：US10098521

申请日：2002-03-18

申请人： Hitoyuki Tagami

发明人： Hitoyuki Tagami

IPC分类号： H03H1116

CPC分类号： H03B27/00

摘要： The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

摘要翻译： 多相信号发生器包括对输入信号增加第一预定相位延迟的第一延迟电路，产生具有根据输入到一个端子的输入信号之间的相位差规定的输出相位的第一输出信号的第一相位内插电路 以及输入到从所述延迟加法单元输出的所述第一输出信号生成单元的另一端子的信号;以及第二相位插值电路，其生成具有根据所述延迟加法单元规定的输出相位的第二输出信号 输入到从延迟加法单元输出的第二输出信号生成单元的一个端子的信号与输入到第二输出信号生成单元的另一端子的输入信号的反相信号之间的相位差。

公开(公告)号：US06384653B1

公开(公告)日：2002-05-07

申请号：US09644188

申请日：2000-08-22

申请人： Steve M. Broome

发明人： Steve M. Broome

IPC分类号： H03H1116

CPC分类号： H03K5/13 ,  H03K5/08 ,  H03K5/1565 ,  H03K2005/00208

摘要： Method and system for providing a signal with a controllable zero crossing time value. The system provides first and second two-sided triangular wave signals, identical but shifted by a selected fraction f·T of a period T of either triangular signal, and forms a weighted sum of the signals, weighted by A and 1−A, respectively, with 0≦A≦1. In each of two time regions within a period T, a zero crossing time of the sum varies linearly with choice of the value A.

摘要翻译： 用于提供具有可控零交叉时间值的信号的方法和系统。 该系统提供第一和第二双面三角波信号，其相同但是移动三角形信号的周期T的选定分数fT，并且分别由A和1-A加权的信号的加权和分别与 0 <= A <= 1。 在周期T内的两个时间区域的每一个中，总和的零交叉时间随着值A的选择而线性变化。