Positive logic digitally tunable capacitor

    公开(公告)号:US11290087B2

    公开(公告)日:2022-03-29

    申请号:US16653728

    申请日:2019-10-15

    申请人: pSemi Corporation

    发明人: Tero Tapio Ranta

    摘要: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

    CAPLESS IMPEDANCE TUNER
    2.
    发明申请

    公开(公告)号:US20210044308A1

    公开(公告)日:2021-02-11

    申请号:US16986814

    申请日:2020-08-06

    发明人: William J. DOMINO

    摘要: A capless impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

    Calibrating an injection locked oscillator

    公开(公告)号:US10855296B2

    公开(公告)日:2020-12-01

    申请号:US16585689

    申请日:2019-09-27

    摘要: A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.

    Positive logic digitally tunable capacitor

    公开(公告)号:US10476484B2

    公开(公告)日:2019-11-12

    申请号:US15871643

    申请日:2018-01-15

    申请人: pSemi Corporation

    发明人: Tero Tapio Ranta

    摘要: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

    SWITCH ASSEMBLY WITH INTEGRATED TUNING CAPABILITY

    公开(公告)号:US20190097326A1

    公开(公告)日:2019-03-28

    申请号:US16197908

    申请日:2018-11-21

    摘要: A multiport RF switch assembly with integrated impedance tuning capability is described that provides a single RFIC solution to switch between transmit and receive paths in a communication system. Dynamic tuning is integrated into each switch sub-assembly to provide the capability to impedance match antennas or other components connected to the multiport switch. The tuning function at the switch can be used to shape the antenna response to provide better filtering at the switch/RF front-end (RFFE) interface to allow for reduced filtering requirements in the RFFE. Memory is designed into the multiport switch assembly, allowing for a look-up table or other data to reside with the switch and tuning circuit. The resident memory will result in easier integration of the tunable switch assembly into communication systems.

    CIRCUITS FOR SWITCHED CAPACITOR RECEIVER FRONT-ENDS

    公开(公告)号:US20180138897A1

    公开(公告)日:2018-05-17

    申请号:US15573385

    申请日:2016-05-11

    IPC分类号: H03J3/08 H03J5/24

    CPC分类号: H03J3/08 H03J5/24

    摘要: Switched capacitor radio frequency receiver front-ends are provided, comprising: a plurality of banks, each comprising: a first switch connected to a RF input signal; a sampling capacitor connected to the first switch and to ground; a second switch connected in parallel to the sampling capacitor; and a Gm cell coupled to the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first bank is not the same as the first point in time for a second bank.