公开(公告)号：US20240313778A1

公开(公告)日：2024-09-19

申请号：US18184941

申请日：2023-03-16

申请人： Logistics and Supply Chain MultiTech R&D Centre Limited

发明人： Feng LU ,  Jing Jung TANG

IPC分类号： H03K19/0185 ,  H03K3/356 ,  H03K17/10

CPC分类号： H03K19/018521 ,  H03K3/356104 ,  H03K17/102

摘要： A voltage comparator circuit for a power source having an energy harvester and an energy storage. The circuit comprises a first voltage input node and a second voltage input node arranged to respectively receive a first voltage level of a first output of the energy harvester and a voltage level of a second output of the energy storage; an output node arranged to switch in response to a comparison of the first and second first voltage levels; and a plurality of semiconductor junction devices arranged to provide a floating local ground arranged to vary in response to a change of the first and/or the second voltage level, wherein the floating local ground has a voltage level higher than an absolute ground connected to the voltage comparator circuit; wherein the floating local ground is arranged to prevent a breakdown of circuit components due to a voltage difference connected at terminals of each of the circuit component exceeding a breakdown voltage of the respective circuit component.

公开(公告)号：US20240305288A1

公开(公告)日：2024-09-12

申请号：US18441491

申请日：2024-02-14

申请人： Finwave Semiconductor, Inc.

发明人： Raul Alidio

IPC分类号： H03K17/10 ,  H01P1/15

CPC分类号： H03K17/102 ,  H01P1/15

摘要： A stack of transistors having equal voltage division when in the OFF state is disclosed. Rather than utilizing compensation capacitors, the present system varies the gate periphery of the transistors in the stack to achieve the desired voltage division. This may be done by varying the number of gate fingers in each transistor, by varying the gate width of the transistors or a combination of these approaches. This approach results in easier design, routing and simulation, with improved power handling.

公开(公告)号：US20240291479A1

公开(公告)日：2024-08-29

申请号：US18581298

申请日：2024-02-19

申请人： LAPIS Technology Co., Ltd.

发明人： Takatsugu KAI

IPC分类号： H03K17/10 ,  H03K17/687

CPC分类号： H03K17/102 ,  H03K17/687 ,  H03K2217/0036

摘要： A discharge control circuit includes: a first gate voltage output circuit that outputs a first gate voltage supplied to a transistor connected to a capacitive load; a second gate voltage output circuit that outputs a second gate voltage supplied to the transistor; and a switching control circuit that switches supply of the first gate voltage and the second gate voltage to the transistor. The first gate voltage output circuit includes: a voltage supply circuit that supplies a voltage to a gate of the transistor until the transistor changes from an off state to an on state; and a current supply circuit that supplies a current to the gate of the transistor. The second gate voltage output circuit outputs a voltage at a constant level as the second gate voltage. The switching control circuit performs control to supply the second gate voltage after supplying the first gate voltage to the transistor.

公开(公告)号：US12021513B2

公开(公告)日：2024-06-25

申请号：US17939873

申请日：2022-09-07

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Yosuke Ogasawara ,  Takayuki Teraguchi

IPC分类号： H03K17/10 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693

CPC分类号： H03K17/102 ,  H03K17/162 ,  H03K17/6871 ,  H03K17/693

摘要： A semiconductor device includes an input terminal, an output terminal, and a plurality of transistors. The transistors are coupled through serial coupling. The transistors include a first transistor and a second transistor. The first transistor has a first end and a second end. The second transistor has a third end, a fourth end, a first gate, and a first body. The third end is coupled to the second end. The semiconductor device further includes a third transistor and a first diode. The third transistor and the first diode are serially coupled between the first body and the first end. The third transistor includes a second gate coupled to the first gate.

公开(公告)号：US20240204769A1

公开(公告)日：2024-06-20

申请号：US18091343

申请日：2022-12-29

申请人： RichWave Technology Corp.

发明人： Chih-Sheng Chen ,  Hsien-Huang Tsai ,  Meng-Lun Li

IPC分类号： H03K17/10

CPC分类号： H03K17/102 ,  H03K2217/0054

摘要： A switch device includes a first switch unit, a second switch unit, a first sub-switch unit, a second sub-switch unit, a first resistor and a second resistor. The first switch unit is coupled to a radio-frequency terminal and coupled to the second switch unit in cascode. The first sub-switch unit is coupled to the second sub-switch unit in cascode. The first sub-switch unit is further coupled between control terminals of the first switch unit and the second switch unit. The first sub-switch unit is further coupled to a node between the first resistor and the first switch unit. The second sub-switch unit is further coupled to a node between the second resistor and the second switch unit. When the first switch unit and the second switch unit are transitioned, the first sub-switch unit and the second sub-switch unit can be turned on to discharge and/or neutralize accumulated charges.

公开(公告)号：US20240178839A1

公开(公告)日：2024-05-30

申请号：US18483611

申请日：2023-10-10

申请人： KEY FOUNDRY CO., LTD.

发明人： Wanchul KONG ,  Jungho KIM

IPC分类号： H03K19/003 ,  H03K17/10 ,  H03K19/0185

CPC分类号： H03K19/00361 ,  H03K17/102 ,  H03K19/018521

摘要： A bidirectional I/O circuit includes an output post driver configured to control an output signal of a bidirectional pad during a normal mode, a floating N-well network configured to apply a VDD-level bias to the output post driver based on an input signal of the bidirectional pad during a power down mode, and a post driver control circuit configured to set an input voltage level of the output post driver to a VDD level during the power down mode to prevent a leakage current path from being formed through the output post driver. A parasitic diode is formed between the drain of the first PMOS transistor and an N-well of the first PMOS transistor. The N-well of the first PMOS transistor is connected to the floating N-well network, and the source and the N-well of the first PMOS transistor are not physically connected to each other.

公开(公告)号：US20240171170A1

公开(公告)日：2024-05-23

申请号：US18427598

申请日：2024-01-30

申请人： pSemi Corporation

发明人： Ravindranath D. SHRIVASTAVA ,  Fleming LAM ,  Payman SHANJANI

IPC分类号： H03K17/0412 ,  H03K17/10

CPC分类号： H03K17/04123 ,  H03K17/102

摘要： A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

公开(公告)号：US11955964B2

公开(公告)日：2024-04-09

申请号：US17169638

申请日：2021-02-08

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Nitin Agarwal ,  Kunal Suresh Karanjkar ,  Venkata Ramanan R

IPC分类号： H03K17/693 ,  H03F3/72 ,  H03K17/00 ,  H03K17/10

CPC分类号： H03K17/693 ,  H03F3/72 ,  H03K17/005 ,  H03K17/102

摘要： A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

公开(公告)号：US20240072794A1

公开(公告)日：2024-02-29

申请号：US18451212

申请日：2023-08-17

申请人： NXP USA, INC.

发明人： Olivier Tico ,  Pascal Kamel Abouda ,  Nicolas Roger Michel Claude Baptistat

IPC分类号： H03K17/687 ,  H03K17/06 ,  H03K17/10

CPC分类号： H03K17/687 ,  H03K17/063 ,  H03K17/102

摘要： A receiver circuit comprising: an input-pin; a receiver-input-node; a ground-pin; an internal-node that is connected to the input-pin; and a MOSFET. The MOSFET has a conduction channel connected in series between the internal-node and the receiver-input-terminal; and a gate terminal, the voltage at which sets the conductivity of the conduction channel. The receiver circuit also includes an amplifier that: has an input terminal that is connected to the internal-node; and provides a voltage control signal to the gate terminal of the MOSFET such that the voltage at the internal-node with respect to the ground-pin is constant.

公开(公告)号：US20240048060A1

公开(公告)日：2024-02-08

申请号：US18341419

申请日：2023-06-26

申请人： Cypress Semiconductor Corporation

发明人： Jojy JOSE ,  Soon Hwei TAN ,  Hariom RAI ,  Arun KHAMESRA

IPC分类号： H02M3/335 ,  H03K17/691 ,  H02M1/00 ,  H03K17/10 ,  H02M1/08

CPC分类号： H02M3/33592 ,  H03K17/691 ,  H02M1/0045 ,  H03K17/102 ,  H02M1/083 ,  H03K2217/0063 ,  H03K2217/0072

摘要： A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.