DRIVER CIRCUIT
    1.
    发明申请

    公开(公告)号:US20250070772A1

    公开(公告)日:2025-02-27

    申请号:US18455781

    申请日:2023-08-25

    Applicant: Apple Inc.

    Abstract: The present disclosure is directed to circuits and a method for mitigating effects of power supply variations on a driver circuit. For example, the circuit can include a first transistor device with a first source/drain (S/D) terminal and a second S/D terminal. The circuit can also include a second transistor device with a third S/D terminal and a fourth S/D terminal. The driver circuit can further include a resistor device electrically connected between the first and third S/D terminals or between the second and fourth S/D terminals. The resistor device can mitigate variations in a high-level output voltage of the driver circuit due to power supply variations.

    Source follower circuitry including phase shift circuitry

    公开(公告)号:US12237829B2

    公开(公告)日:2025-02-25

    申请号:US18086534

    申请日:2022-12-21

    Applicant: XILINX, INC.

    Abstract: An electronic system includes a source follower circuitry that functions as an input driver. The source follower circuitry includes a first input transistor, first current source circuitry, and first phase shift circuitry. The first input transistor includes a first node coupled to a first voltage node, a second node coupled to a first output node, and a gate node coupled to a first input node. The gate node receives a first input signal via the first input node. The first current source circuitry coupled to the first output node and configured to generate a first bias current. The first phase shift circuitry is coupled to the first current source circuitry. The first phase shift circuitry generates a first phase shift signal to modulate the first current source circuitry to reduce signal drop across the first input transistor.

    Efficient Switching Circuit
    3.
    发明申请

    公开(公告)号:US20250062759A1

    公开(公告)日:2025-02-20

    申请号:US18937120

    申请日:2024-11-05

    Abstract: An apparatus includes a first leg having a plurality of transistors connected in series between a first node and a second node. Each of the plurality of transistors includes a respective body diode. The apparatus further includes a second leg connected between the first node and the second node and in parallel to the series connection of the plurality of transistors of the first leg. The second leg includes a first transistor. The second leg has lower reverse recovery losses relative to the first leg.

    Integrated circuit and method of manufacturing same

    公开(公告)号:US12231117B2

    公开(公告)日:2025-02-18

    申请号:US18346723

    申请日:2023-07-03

    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

    Overdrive I/O ESD Protection Network

    公开(公告)号:US20250055449A1

    公开(公告)日:2025-02-13

    申请号:US18366215

    申请日:2023-08-07

    Abstract: Systems and methods are provided for an electronic device that comprises a core logic circuit coupled to a supply voltage rail and an operating voltage rail. During a standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and a post driver voltage rail has an overdrive voltage that is greater than the operating voltage. The electronic device further comprises a first power clamp circuit coupled to the supply voltage rail and the post driver voltage rail, a low-side logic-high voltage rail coupled to the first end of the core logic circuit, and a first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. The first power-to-power clamp circuit is configured to receive electrostatic discharge (ESD) current between the post driver voltage rail and the low-side logic-high voltage rail.

    Buffer for voltage controlled oscillator (VCO) or other applications

    公开(公告)号:US12224743B2

    公开(公告)日:2025-02-11

    申请号:US18155535

    申请日:2023-01-17

    Abstract: An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

    Sensor arrangement for capacitive position detection of an object

    公开(公告)号:US12221015B2

    公开(公告)日:2025-02-11

    申请号:US17796554

    申请日:2021-01-25

    Abstract: A sensor arrangement for capacitive detection of an object, including: an electrode arrangement having a heating element as an electrode; a detection device providing a detection signal to a sensor electrode and capacitively detecting the presence of an object near the sensor electrode; a high-side switch connected between a heating power source having a first potential and the heating element; a low-side switch connected between the heating element and a second potential; and a gate controller closing the high-side switch and low-side switch in a heating mode and opening the high-side switch and low-side switch in a detection mode. A decoupling MOSFET is connected between the high-side switch and heating element. The gate controller closes the MOSFET in the heating mode and opens the MOSFET in the detection mode. During the detection mode, the decoupling circuit provides a third potential at a first node between the high-side switch and MOSFET.

    INTERLOCK DEVICE, ENERGY STORAGE SYSTEM, CONTROL METHOD, AND DEVICE THEREOF

    公开(公告)号:US20250047129A1

    公开(公告)日:2025-02-06

    申请号:US18722487

    申请日:2022-09-23

    Abstract: The present application provides an interlock device, an energy storage system, a control method, and a control apparatus. The interlock device comprises: a first interlock circuit, a first drive processing circuit, a first drive status feedback circuit, a second interlock circuit, a second drive processing circuit, and a second drive status feedback circuit. The first interlock circuit, the first drive processing circuit, and the first drive status feedback circuit are connected, and the second interlock circuit, the second drive processing circuit, and the second drive status feedback circuit are connected. The first interlock circuit receives an output of the second drive status feedback circuit, and the second interlock circuit receives an output of the first drive status feedback circuit, thereby forming an interlock circuit.

Patent Agency Ranking