公开(公告)号：US20240348251A1

公开(公告)日：2024-10-17

申请号：US18498852

申请日：2023-10-31

申请人： SK hynix Inc.

发明人： Ji Hyo KANG ,  Hyun Bae LEE

IPC分类号： H03K19/00 ,  H03K17/687

CPC分类号： H03K19/0005 ,  H03K17/6877

摘要： A buffer circuit may include a buffer unit including a first resistor connected between a power source terminal and a first node, a first inductor set connected between the first node and a first input terminal, a second resistor connected between the power source terminal and a second node, and a second inductor set connected between the second node and a second input terminal, and a first variable capacitance circuit connected between the first node and the second node, and configured to adjust a first capacitance value according to a plurality of first adjustment signals.

公开(公告)号：US12113527B2

公开(公告)日：2024-10-08

申请号：US17886473

申请日：2022-08-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chang-Ting Wu

IPC分类号： H03K19/00 ,  H03K19/0185

CPC分类号： H03K19/0005 ,  H03K19/018557

摘要： An off-chip driver (OCD), including a pull-up driver and a pull-down driver, is provided. The pull-up driver and the pull-down driver are coupled to an output pad. One of the pull-up driver and the pull-down driver includes a main driving circuit, an auxiliary driving circuit, a connection circuit, and a common impedance. The main driving circuit is used to perform an output driving operation on the output pad, and the auxiliary driving circuit is used to selectively perform the output driving operation on the output pad. A first terminal of the common impedance is coupled to a driving terminal of the main driving circuit and a driving terminal of the auxiliary driving circuit through the connection circuit. A second terminal of the common impedance is coupled to the output pad.

公开(公告)号：US20240313777A1

公开(公告)日：2024-09-19

申请号：US18674934

申请日：2024-05-27

申请人： SK hynix Inc.

发明人： Seung Ho LEE

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/017 ,  H03K19/17788

CPC分类号： H03K19/00315 ,  H03K19/0005 ,  H03K19/01742 ,  H03K19/17788

摘要： A memory system may include a memory device and a memory controller. The memory device may be configured to store data. The memory controller may be configured to communicate with the memory device by an input/output driving circuit. The input/output driving circuit comprises a pull-down driver and a gate control logic. The pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. The gate control logic including a third transistor and a fourth transistor which are electrically coupled 10 between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. The source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.

公开(公告)号：US12081214B2

公开(公告)日：2024-09-03

申请号：US18054032

申请日：2022-11-09

申请人： MEDIATEK INC.

发明人： Kin-Hooi Dia ,  Ssu-Yen Wu ,  Shih-Yun Lin

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

公开(公告)号：US12081213B1

公开(公告)日：2024-09-03

申请号：US17829127

申请日：2022-05-31

申请人： Ceremorphic, Inc.

发明人： Akshaykumar Salimath ,  Sanghamitra Debroy ,  Venkat Mattela

IPC分类号： H03K19/00 ,  H03K19/08

CPC分类号： H03K19/0008 ,  H03K19/08

摘要： A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. Nanotrack along the second axis extend beyond the central portion to define an output portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis and the second axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the output portion and indicates a first value when skyrmion is present.

公开(公告)号：US20240291490A1

公开(公告)日：2024-08-29

申请号：US18398917

申请日：2023-12-28

申请人： c/o Sharp Semiconductor Innovation Corporation

发明人： Haruhiko SHIGEMASA

IPC分类号： H03K19/0185 ,  H03K3/012 ,  H03K19/00

CPC分类号： H03K19/018514 ,  H03K3/012 ,  H03K19/0016

摘要： An electronic circuit includes the following: a first circuit configured to generate a first output having a first voltage-rise time; a second circuit configured to vary, in accordance with data included in challenge data, the first output to a second output having a second voltage-rise time different from the first voltage-rise time; and a third circuit in which an initial value is inconstant, and in which an output value varies in accordance with the second voltage-rise time.

公开(公告)号：US20240275644A1

公开(公告)日：2024-08-15

申请号：US18569660

申请日：2021-12-28

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： TAKUNARI HATTORI ,  TATSUYA SAKAE ,  JUNICHIRO SHIRAI

IPC分类号： H04L25/02 ,  H03K19/00 ,  H03K19/0175

CPC分类号： H04L25/0292 ,  H03K19/0005 ,  H03K19/017581 ,  H04L25/0276

摘要： A power supply noise is suppressed while power consumption or current consumption in a data transmission circuit is reduced.
The data transmission circuit includes first and second drive circuits and an operation state control circuit. The first drive circuit drives first data that transitions or does not transition in synchronization with a clock signal. The second drive circuit drives second data that transitions at a timing when the first data does not transition in synchronization with the clock signal. The operation state control circuit individually controls operation states of the first and second drive circuits.

公开(公告)号：US20240275384A1

公开(公告)日：2024-08-15

申请号：US18644156

申请日：2024-04-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： GREG GRUBER ,  CHI-LIN LIU ,  MING-CHANG KUO ,  LEE-CHUNG LU ,  SHANG-CHIH HSIEH

IPC分类号： H03K19/00 ,  G01R31/3185

CPC分类号： H03K19/0013 ,  G01R31/318536

摘要： An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

公开(公告)号：US12063034B2

公开(公告)日：2024-08-13

申请号：US17823401

申请日：2022-08-30

申请人： KANDOU LABS SA

发明人： Armin Tajalli

IPC分类号： H03K17/687 ,  H03K19/00 ,  H04L12/40

CPC分类号： H03K17/6872 ,  H03K19/0005 ,  H04L12/40 ,  H03K2217/0063 ,  H03K2217/0072

摘要： Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.

公开(公告)号：US12057831B2

公开(公告)日：2024-08-06

申请号：US17626719

申请日：2020-07-10

申请人： Arizona Board of Regents on behalf of Arizona State University ,  The Texas A&M University System

发明人： Sarma Vrudhula ,  Sunil Khatri

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/28 ,  G11C16/34 ,  H03K19/00 ,  G11C29/32

CPC分类号： H03K19/0027 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3404 ,  G11C29/32

摘要： Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.