公开(公告)号：US20230155590A1

公开(公告)日：2023-05-18

申请号：US17916816

申请日：2021-04-07

申请人： Technion Research & Development Foundation Limited

发明人： Shahar KVATINSKY ,  Barak HOFFER ,  Eilam YALON ,  Nicolas WAINSTEIN

IPC分类号： H03K19/02 ,  G11C13/00

CPC分类号： H03K19/02 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

摘要： An electronic memory block comprises phase change memory cells for memory storage and further phase change memory cells forming logic gates, to provide in-memory data processing.

公开(公告)号：US11108387B2

公开(公告)日：2021-08-31

申请号：US16725061

申请日：2019-12-23

申请人： LONTIUM SEMICONDUCTOR CORPORATION

发明人： Xiangyu Ji ,  Cheng Tao ,  Yu Chen ,  Feng Chen ,  Jiaxi Fu ,  Haiyan Wei

IPC分类号： H03K17/04 ,  H03K19/20 ,  H03K19/02

摘要： A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

公开(公告)号：US11031937B2

公开(公告)日：2021-06-08

申请号：US16606436

申请日：2018-04-17

申请人： King Abdullah University of Science and Technology

发明人： Karumbaiah Chappanda Nanaiah ,  Mohammad Ibrahim Younis

IPC分类号： H03K19/21 ,  H03K19/02

摘要： Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro-cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

公开(公告)号：US20210111723A1

公开(公告)日：2021-04-15

申请号：US16606436

申请日：2018-04-17

申请人： King Abdullah University of Science and Technology

发明人： Karumbaiah Chappanda NANAIAH ,  Mohammad Ibrahim YOUNIS

IPC分类号： H03K19/21 ,  H03K19/02

摘要： Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro-cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

公开(公告)号：US10608633B1

公开(公告)日：2020-03-31

申请号：US16553590

申请日：2019-08-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Russell Schreiber

IPC分类号： H03K19/00 ,  H03K19/02 ,  H03K19/0175 ,  H04L25/20

摘要： An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

公开(公告)号：US20190341920A1

公开(公告)日：2019-11-07

申请号：US16332150

申请日：2017-09-21

申请人： KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY

发明人： Saad ILYAS ,  Md Abdullah Al HAFIZ ,  Hossein FARIBORZI ,  Mohammad Ibrahim YOUNIS

IPC分类号： H03K19/02 ,  H03H9/02 ,  H03H9/24 ,  H03K19/20 ,  H03K19/21

摘要： A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

公开(公告)号：US20180351344A1

公开(公告)日：2018-12-06

申请号：US15778106

申请日：2016-08-23

申请人： KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO

发明人： Daisuke AOKI

IPC分类号： H02H3/087 ,  H02H7/20 ,  H03K17/082 ,  H03K17/687 ,  H03K19/003 ,  H03K19/02

CPC分类号： H02H3/087 ,  H02H7/20 ,  H03K17/00 ,  H03K17/08 ,  H03K17/687

摘要： A drive circuit includes plural drive transistors that drive plural load elements, and an operation limiting circuit. The operation limiting circuit is configured by a logic circuit combining AND elements and NOR elements. When plural control signals are input to the operation limiting circuit due to abnormal input, the plural drive transistors for which the control signals were input are switched OFF.

公开(公告)号：US09576094B2

公开(公告)日：2017-02-21

申请号：US14464366

申请日：2014-08-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Chi-Chuan Chuang ,  Yi-Hsiang Lai ,  Jie-Hong Chiang

IPC分类号： G06F17/50 ,  H03K19/00 ,  H03K19/04 ,  H03K19/096 ,  H03K19/02

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5054 ,  G06F17/5059 ,  G06F2217/06 ,  G06F2217/84 ,  H03K19/00 ,  H03K19/02 ,  H03K19/04 ,  H03K19/0948 ,  H03K19/0966

摘要： A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

摘要翻译： 逻辑电路包括第一和第二输入，输出，输入确认节点，输出确认节点，逻辑评估块，预充电电路和完成检测电路。 逻辑评估块在第一和第二输入端执行第一和第二输入信号的逻辑评估，并输出对应于逻辑评估的输出信号。 预充电电路响应于输入确认节点处的第一输入信号和确认信号，对逻辑评估块进行预充电。 完成检测电路响应于第二输入信号和输出信号在输出确认节点产生确认信号。

公开(公告)号：US09548741B1

公开(公告)日：2017-01-17

申请号：US14798485

申请日：2015-07-14

申请人： Technion Research and Development Foundation LTD.

发明人： Shahar Kvatinsky ,  Avinoam Kolodny ,  Yifat Hanein

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/02 ,  H03K19/094

CPC分类号： H03K19/1776 ,  G11C13/0007 ,  H03K19/02 ,  H03K19/094 ,  H03K19/17708

摘要： A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.

摘要翻译： 一种包括忆阻阿克斯逻辑阵列的装置，其中忆阻Akers逻辑阵列包括彼此耦合的多个基本逻辑单元; 其中每个基元逻辑单元包括至少一个忆阻器件。

公开(公告)号：US09501600B2

公开(公告)日：2016-11-22

申请号：US14051881

申请日：2013-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC分类号： G06F17/50 ,  H03K19/02 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/02

摘要： An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.

摘要翻译： 通过具有金属线的标称最小间距的预定制造工艺制造集成电路。 集成电路包括沿着第一方向延伸的多条金属线和多条金属线下的多个标准单元。 多个金属线在与第一方向垂直的第二方向上以标称最小间距的整数倍分开。 多个标准单元包括被配置为执行预定功能并具有第一布局的第一标准单元和被配置为执行预定功能并且具有与第一布局不同的第二布局的第二标准单元。 第一和第二标准单元沿着第二方向具有单元高度（H），单元高度是标称最小间距的非整数倍。