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    PROGRAMMABLE LOGIC DEVICES WITH MULTI-LEVEL INPUT/OUTPUT SIGNALS
    1.
    发明公开
    PROGRAMMABLE LOGIC DEVICES WITH MULTI-LEVEL INPUT/OUTPUT SIGNALS 审中-公开

    公开(公告)号：US20240364344A1

    公开(公告)日：2024-10-31

    申请号：US18140359

    申请日：2023-04-27

    申请人： Hewlett Packard Enterprise Development LP

    发明人： Rachid Kadri ,  Michael Chan

    IPC分类号： H03K19/173 ,  H03K19/20 ,  H03M1/78

    CPC分类号： H03K19/173 ,  H03K19/20 ,  H03M1/785

    摘要： One aspect provides a programmable logic device. The device includes an input circuit for detecting a multi-level input signal and an output circuit. The input circuit includes: an input pin for receiving the multi-level input signal; first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals; a pair of comparators, each comparator having a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators. The output circuit includes a third programmable voltage generator to generate a third multi-level voltage signal, an output pin, and a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.

    Operation stage of pipeline analog-to-digital converter (ADC) and multiplying circuit thereof
    5.
    发明公开
    Operation stage of pipeline analog-to-digital converter (ADC) and multiplying circuit thereof 审中-公开

    公开(公告)号：US20240283456A1

    公开(公告)日：2024-08-22

    申请号：US18420801

    申请日：2024-01-24

    申请人： REALTEK SEMICONDUCTOR CORPORATION

    发明人： SHIH-HSIUNG HUANG

    IPC分类号： H03K19/173 ,  H03K17/687

    CPC分类号： H03K19/1737 ,  H03K17/6872

    摘要： A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

    Programmable logic circuit device and image processing apparatus
    6.
    发明授权
    Programmable logic circuit device and image processing apparatus 有权

    公开(公告)号：US12057835B2

    公开(公告)日：2024-08-06

    申请号：US17315387

    申请日：2021-05-10

    申请人： FUJIFILM Business Innovation Corp.

    发明人： Fumiaki Sugiyama

    IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/17748

    CPC分类号： H03K19/17748 ,  H03K19/1733

    摘要： A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements. The processor is configured to: upon detection of an abnormality while performing processing in a state in which the elements in the reconfiguration regions are connected in accordance with reconfiguration data designating connection between the elements in the reconfiguration regions, acquire reconfiguration data designating such connection between the elements that the processing being performed is not performed; and change connection between the elements in the reconfiguration regions in accordance with the designation by the acquired reconfiguration data.

    FPGA neighbor output mux direct connections to minimize routing hops
    7.
    发明授权
    FPGA neighbor output mux direct connections to minimize routing hops 有权

    公开(公告)号：US12052160B2

    公开(公告)日：2024-07-30

    申请号：US17650960

    申请日：2022-02-14

    申请人： EFINIX, INC.

    发明人： Marcel Gort ,  Brett Grady

    IPC分类号： H03K19/17728 ,  H03K19/173 ,  H04L45/122 ,  H04L45/42

    CPC分类号： H04L45/122 ,  H03K19/1737 ,  H03K19/17728 ,  H04L45/42

    摘要： Methods and apparatuses to provide FPGA neighbor output mux direct connections to reduce, and potentially minimize, routing hops are described. Embodiments described herein include the addition of direct connections from one tile to the output muxing of a neighboring tile. An FPGA apparatus includes a plurality of logic block tiles. One or more direct connections extend from one or more logic block tiles of the plurality of logic block tiles to one or more inputs of output multiplexors (muxes) of one or more neighboring logic block tiles. The one or more direct connections are configured to drive one or more wires that start at the one or more neighboring logic block tiles.

    Device, system and method to detect clock skew
    8.
    发明授权
    Device, system and method to detect clock skew 有权

    公开(公告)号：US12050483B2

    公开(公告)日：2024-07-30

    申请号：US17021900

    申请日：2020-09-15

    申请人： Intel Corporation

    发明人： Yossi Ben Simon ,  Ariel Avital ,  Arkady Vaisman ,  Ernest Knoll

    IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K19/173 ,  H03K19/20

    CPC分类号： G06F1/10 ,  H03K19/1737 ,  H03K19/20

    摘要： Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

    High speed differential rom
    9.
    发明授权
    High speed differential rom 有权

    公开(公告)号：US12027229B2

    公开(公告)日：2024-07-02

    申请号：US17877954

    申请日：2022-07-31

    申请人： Texas Instruments Incorporated

    发明人： Suresh Balasubramanian ,  David J. Toops

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

    CPC分类号： G11C7/062 ,  G11C7/1069 ,  G11C7/12 ,  H03K19/1737

    摘要： A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.