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    DYNAMIC DIVIDER HAVING INTERLOCKING CIRCUIT
    1.
    发明申请
    DYNAMIC DIVIDER HAVING INTERLOCKING CIRCUIT 有权
    具有互锁电路的动力分流器

    公开(公告)号：US20140376683A1

    公开(公告)日：2014-12-25

    申请号：US13926923

    申请日：2013-06-25

    申请人： QUALCOMM Incorporated

    发明人： Jeremy Mark Goldblatt ,  Devavrata Vasant Godbole ,  Hsuanyu Pan

    IPC分类号： H03K21/17

    CPC分类号： H03K21/17 ,  H03K5/15033 ,  H03K23/425

    摘要： A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.

    摘要翻译： 高速和低功率分配器包括四个动态锁存器环，互锁电路和四个输出反相器。 每个锁存器具有第一动态节点M和第二动态节点N.互锁电路耦合到M个节点。 基于接收到的一个或多个M个节点信号，互锁电路选择性地控制M个模式中的一个或多个的逻辑值，使得随着时间的推移，当分频器被计时时，N个节点上的信号中只有一个为低 在给定的时间。 输出反相器产生从分频器输出的N个节点信号的反相版本，作为低相位噪声25％占空比输出信号I，IB，Q和QB。 在一个具体示例中，每个锁存器具有八个晶体管，不超过八个晶体管。 分离器快速自动地从错误的状态干扰中恢复。

    Mulit-Phase Frequency Divider Having One or More Delay Latches
    2.
    发明申请
    Mulit-Phase Frequency Divider Having One or More Delay Latches 有权
    具有一个或多个延迟锁存器的多相分频器

    公开(公告)号：US20130328600A1

    公开(公告)日：2013-12-12

    申请号：US13493400

    申请日：2012-06-11

    申请人： Joachim Heinz Dieter Woelk ,  Erwin Robert Schlag

    发明人： Joachim Heinz Dieter Woelk ,  Erwin Robert Schlag

    IPC分类号： H03K21/17

    CPC分类号： H03K21/023 ,  H03K23/42

    摘要： A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.

    摘要翻译： 多相分频器包括被配置为接收具有第一频率和第一相位的第一输入时钟的第一和第二锁存器，其中第二锁存器接收反相的第一输入时钟。 第一和第二锁存器产生多个输出时钟，每个输出时钟的频率等于第一个频率除以预定的分频比。 多个输出时钟各自具有与第一阶段交错的不同相位。 分频器还包括电连接在第一和第二锁存器之间的至少第一延迟锁存器。 第一延迟锁存器被配置为基于由第一锁存器产生的输出时钟和在第一频率和第二相位的第二输入时钟产生两个延迟的输出时钟。 这两个延迟输出时钟的频率等于第一频率除以具有不同交错相位的预定比率。

    Logic coincidence gate, triplet of logic gates and sequential logic circuit using this logic gate
    3.
    发明授权
    Logic coincidence gate, triplet of logic gates and sequential logic circuit using this logic gate 失效
    逻辑门，逻辑门的三元组和使用该逻辑门的顺序逻辑电路

    公开(公告)号：US4748347A

    公开(公告)日：1988-05-31

    申请号：US918877

    申请日：1986-10-15

    申请人： Pham N. Tung

    发明人： Pham N. Tung

    IPC分类号： H03K19/0952 ,  H03K19/21 ,  H03K23/40 ,  H03K23/66 ,  H03K19/094 ,  H03K19/096 ,  H03K21/17 ,  H03K27/00

    CPC分类号： H03K19/0952 ,  H03K19/217 ,  H03K23/40 ,  H03K23/667

    摘要： The invention pertains to programmable fast logic.The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level.Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.

    摘要翻译： 本发明涉及可编程快速逻辑。 本发明的逻辑门包括两个并联安装的反相器，包括一个晶体管和一个饱和负载。 第二反相器通过晶体管供电，晶体管的电极栅极连接到漏极，其连接到第一反相器的漏极，第一反相器的漏极可以具有额外的输入（OR功能）。 三个串联安装的逻辑门的三元组包括在第三个门处的编程输入，重新循环输出，在三阶组序列的情况下，在第一个三元组的第一个门处重新输入。 可编程逻辑电路通过一系列串联安装的三元组获得，它们全部环回到序列的第一个栅极。 通过将一个或两个编程输入置于逻辑0电平获得编程。 应用：可编程分频器电路，其中比率彼此依次相继。

    CMOS binary counter
    5.
    发明授权
    CMOS binary counter 失效
    CMOS二进制计数器

    公开(公告)号：US4759043A

    公开(公告)日：1988-07-19

    申请号：US33381

    申请日：1987-04-02

    申请人： Edward T. Lewis

    发明人： Edward T. Lewis

    IPC分类号： H03K23/00 ,  H03K3/356 ,  H03K21/17 ,  H03K23/40 ,  H03K23/50 ,  H03K23/52 ,  H03K23/44

    CPC分类号： H03K3/356104 ,  H03K21/17 ,  H03K23/52

    摘要： A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

    摘要翻译： 具有200MHz时钟速率的1.2μmCMOS二进制计数器包括可以连接在多个4位部分中的4位计数部分。 4位计数器部分中的每个位级都使用这种级的当前状态来确定在下一级中发生了什么。 每个4位部分通过添加最低阶进位位输入的连续处理来执行计数功能。 计数使能信号用于启用计数过程以及用作到第一级的进位位输入。 当处于逻辑“零”状态时，计数使能会影响计数器复位。 一旦计数使能提高到逻辑“1”状态，计数过程就从第一个时钟脉冲的上升沿开始。 只要保持计数使能，继续计数。 当计数使能降低到“零”状态时，计数结束，计数器复位发生在时钟的下一个顺序上升沿。

    Dynamic divider having interlocking circuit
    7.
    发明授权
    Dynamic divider having interlocking circuit 有权
    动态分配器具有互锁电路

    公开(公告)号：US09088285B2

    公开(公告)日：2015-07-21

    申请号：US13926923

    申请日：2013-06-25

    申请人： QUALCOMM Incorporated

    发明人： Jeremy Mark Goldblatt ,  Devavrata Vasant Godbole ,  Hsuanyu Pan

    IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K21/17 ,  H03K5/15 ,  H03K23/42

    CPC分类号： H03K21/17 ,  H03K5/15033 ,  H03K23/425

    摘要： A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.

    摘要翻译： 高速和低功率分配器包括四个动态锁存器环，互锁电路和四个输出反相器。 每个锁存器具有第一动态节点M和第二动态节点N.互锁电路耦合到M个节点。 基于接收到的一个或多个M个节点信号，互锁电路选择性地控制M个模式中的一个或多个的逻辑值，使得随着时间的推移，当分频器被计时时，N个节点上的信号中只有一个为低 在给定的时间。 输出反相器产生从分频器输出的N个节点信号的反相版本，作为低相位噪声25％占空比输出信号I，IB，Q和QB。 在一个具体示例中，每个锁存器具有八个晶体管，不超过八个晶体管。 分离器快速自动地从错误的状态干扰中恢复。