公开(公告)号：US06661864B2

公开(公告)日：2003-12-09

申请号：US09929119

申请日：2001-08-15

申请人： Masahiko Ishiwaki

发明人： Masahiko Ishiwaki

IPC分类号： H03K2140

CPC分类号： H03K21/40

摘要： A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

公开(公告)号：US06470064B2

公开(公告)日：2002-10-22

申请号：US09973147

申请日：2001-10-08

申请人： Michael K. Carpenter

发明人： Michael K. Carpenter

IPC分类号： H03K2140

CPC分类号： H03K23/50 ,  H03K21/16

摘要： A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate. Accordingly, counter chains of unlimited size that can be implemented in a field programmable logic array (FPGA) and that can run at the maximum clock rate of the FPGA can be realized.

摘要翻译： 同步计数器，本发明的计数器与时钟（例如，FPGA的主时钟）同步，并且包括响应于主时钟递增的第一计数器，从第一计数器接收计数器位的再同步器，并且在适当时 产生增量信号，以及由主时钟计时的响应于增量信号递增的第二计数器。 在优选实施例中，再同步器是与计数器位中的至少一个选择的一个和与门锁（其中第一计数器是n位计数器）的n位AND门，锁存器例如触发器锁存输出 的和门。 因此，使用以主时钟速率（即与计数器链相同的速率）触发的触发器将小计数链链接在一起，以形成将以主时钟速率起作用的任何长度的反向链。 因此，可以实现可以在现场可编程逻辑阵列（FPGA）中实现并且可以以FPGA的最大时钟速率运行的无限大小的反向链。