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公开(公告)号：US4119867A
公开(公告)日：1978-10-10
申请号：US708188
申请日：1976-07-23
申请人： Shigeru Morokawa , Yukio Hashimoto
发明人： Shigeru Morokawa , Yukio Hashimoto
IPC分类号： H03K23/52 , G04G3/02 , G11C19/18 , H03K23/40 , H03K23/54 , H03K25/02 , H03K23/02 , H03K17/60
CPC分类号： H03K23/40 , G04G3/02 , G11C19/184 , H03K25/02
摘要： An odd number of inverting memory blocks are connected in series in a closed ring circuit. Each inverting elememt comprises a P channel field effect transistor and an N channel field effect transistor which are connected in parallel opposition. Control signals of the same phase are applied to the gate electrodes of the P and N channel field effect transistors. An inverter circuit comprising a pair of field effect transistors having gate electrodes is connected to one of two parallel connected, conductive electrodes of a temporary memory switching circuit. Control gate electrodes of the inverting memory block are controlled by control signals having the same phase and at a frequency to be divided for producing a frequency divided output from the output of one of the inverting memory blocks.
摘要翻译： 奇数个反相存储器块串联连接在闭环电路中。 每个反相元件包括平行相对连接的P沟道场效应晶体管和N沟道场效应晶体管。 将相同相位的控制信号施加到P沟道场效应晶体管和N沟道场效应晶体管的栅电极。 包括具有栅电极的一对场效应晶体管的逆变器电路连接到临时存储器开关电路的两个并联连接的导电电极中的一个。 反相存储器块的控制栅电极由具有相同相位和待分频的控制信号控制，以产生从反转存储器块之一的输出的分频输出。
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公开(公告)号：US3746886A
公开(公告)日：1973-07-17
申请号：US3746886D
申请日：1971-10-15
发明人： KONOPKA J
CPC分类号： H03J5/0218 , H03J5/0227 , H03J5/0236 , H03K17/9645
摘要： A triggered neon lamp memory circuit selectively produces control voltages for an electrically controlled rado wave receiver. Each stage comprises a neon lamp, a transistor and a control voltage potentiometer coupled in series between a common source of sustaining potential and a point of reference potential. When the neon lamp of a given stage is triggered, the associated transistor is turned on to effectively couple a fixed voltage to the control voltage potentiometer. When the neon lamp turns off, the transistor turns off to remove the fixed voltage from the control voltage potentiometer while, at the same time, enabling the voltage at one terminal of the neon lamp to remain substantially above the reference potential to thereby reduce the voltage across the neon lamp to a point substantially below the trigger level. In one embodiment, the neon lamp of any one stage is triggered on by temporarily coupling a trigger potential to the neon lamp by manually actuating a touch contact. The triggering of any one lamp lowers the common sustaining potential to thereby extinguish the neon lamp of the previously activated stage. In another embodiment, a shifting circuit, either remotely or locally activated, successively triggers each lamp so that the circuit functions in the nature of a ring counter. In the remote control embodiment, programming means are provided to cause the shifting circuit to selectively prefer preselected ones of the plurality of stages by providing a greater selection period therefor.
摘要翻译： 触发的氖灯存储器电路选择性地产生用于电控雷达接收器的控制电压。 每个级包括氖灯，晶体管和控制电压电位器，串联耦合在共同的维持电位和参考电位之间。 当给定阶段的氖灯被触发时，关联的晶体管被接通以有效地将固定电压耦合到控制电压电位器。 当氖灯关闭时，晶体管关闭，以从控制电压电位器去除固定电压，同时使氖灯的一个端子处的电压保持在基准电位以上，从而降低电压 穿过霓虹灯至大大低于触发电平的点。 在一个实施例中，通过手动致动触摸触点将触发电位临时耦合到氖灯来触发任何一个级的氖灯。 任何一个灯的触发降低了常见的维持电位，从而熄灭先前激活的阶段的氖灯。 在另一个实施例中，远程或局部激活的移位电路连续地触发每个灯，使得电路在环形计数器的性质上起作用。 在遥控实施例中，提供编程装置，以通过提供更大的选择周期来使移位电路有选择地更喜欢多级中的预先选择的级。
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公开(公告)号：US3681574A
公开(公告)日：1972-08-01
申请号：US3681574D
申请日：1970-03-30
申请人： AVERY LTD W & T
CPC分类号： H04M1/2725
摘要： A circuit for serially entering information into a shift register which avoids the need to re-set the register with a previous or subsequent separate re-setting operation, comprising a sensing circuit responsive to each of a sequence of operations of an encoder, and a timing switch which is under the control of the sensing circuit so as to be operative on a operation of the encoder to clear from the shift register information related to a next preceding operation of the encoder after a pre-determined time interval has elapsed from this preceding operation.
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公开(公告)号：US3596065A
公开(公告)日：1971-07-27
申请号：US3596065D
申请日：1968-11-07
申请人： IBM
摘要： A method and apparatus for rate detection of the ratio of first events to second events in a stream of basic events where each event in the stream of basic events must either be a first event or second event. The method provides an indication of the average of the quantized log to the base two of the number of first events that occurs between the occurrence of second events. The apparatus comprises a binary counter, a shift register, a digital to analog converter alarm and metering logic.
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公开(公告)号：US3857102A
公开(公告)日：1974-12-24
申请号：US33213873
申请日：1973-02-13
申请人： ZIBIN D
发明人： ZIBIN D
CPC分类号： H03K21/00
摘要： A pulse counter including AND, OR, NOT gates and their combinations comprises two n-stage flip-flops, where n 5, 6, ..... , the outputs of the first one of these flip-flops being connected through a first group of n AND gates to the inputs of the other flip-flop, the outputs of the latter being connected through a second group of n AND gates to the inputs of the first flip-flop. The other inputs of the AND gates in each group are interconnected and form the respective count inputs of the counter. In the n-stage flip-flops of the counter the output of each one of the n stages is connected to the inputs of s other inputs of the same flip-flop, and each one of the inputs of each said flip-flop is connected to the inputs of s stages of the same flip-flop, where 2 > OR = s > OR = n-3.
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公开(公告)号：US3733471A
公开(公告)日：1973-05-15
申请号：US3733471D
申请日：1971-12-07
申请人： NCR CO
发明人： GILBERG R
IPC分类号： H03K19/096 , H03K23/44 , H03K23/66 , H03K21/36 , H03K23/02
CPC分类号： H03K19/096 , H03K23/44 , H03K23/66
摘要： A four phase MOS-LSI dynamic recirculating binary counter which operates in an N bit time cycle and which counts in excess of 2N 1 counts is disclosed. The counter includes an N stage shift register counter and output logic. The output logic includes a latch which is set once each time cycle during a given bit time and reset by the first logic 0 signal from the shift register counter. If during the given bit time of the next cycle the latch is still set and the least significant shift register stage signal is logic 1, a signal is provided to set additional latch circuits which act as additional stages of the binary counter.
摘要翻译： 公开了以N位时间周期运行并且计数超过2N-1个计数的四相MOS-LSI动态循环二进制计数器。 该计数器包括N级移位寄存器计数器和输出逻辑。 输出逻辑包括一个锁存器，该锁存器在给定位时间期间每一个时间周期被设置一次，并由来自移位寄存器计数器的第一逻辑0信号复位。 如果在下一周期的给定比特时间期间，锁存器仍然被设置，并且最低有效移位寄存器级信号是逻辑1，则提供一个信号以设置用作二进制计数器的附加级的附加锁存电路。
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公开(公告)号：US3629710A
公开(公告)日：1971-12-21
申请号：US3629710D
申请日：1970-12-16
发明人： DURLAND DOUGLAS H
摘要： A digitally controlled pulse generator whose duty cycle may be rapidly and accurately varied to supply a load with a required amount of power including a data register, a recirculating counter, a coincidence detector connected to the memory unit and the recirculating counter for providing an output signal when the count stored in the memory unit coincides with that in the recirculating counter and a bistable storage element having one input connected to the coincidence detector and a second input connected to the counter such that the storage element is set in one state each time the coincidence detector provides an output signal and in the other state each time the counter recycles to zero.
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公开(公告)号：US3613014A
公开(公告)日：1971-10-12
申请号：US3613014D
申请日：1969-09-11
发明人： MOEGEN GERHARD D
摘要： A check circuit for a ring counter of the electronic type. The check circuit continually monitors the ring counter and determines when an abnormal condition occurs, i.e., when more than one stage of the counter is in a ''''1'''' condition and also when no stages of the counter are in the ''''1'''' condition. A separate subcircuit is provided for each half of the ring counter and each such subcircuit determines whether at least one of the stages in the respective half of the counter is in the ''''1'''' condition. Since one, and only one, of the stages should at any time be in its ''''1'''' condition, the normal condition then is for only one of the subcircuits to be responsive to its respective group of counter stages. When both of the subcircuits, or none, is providing an output, this is an indication of abnormal operation, and a distinctive output signal is provided.
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公开(公告)号：US4464774A
公开(公告)日：1984-08-07
申请号：US358366
申请日：1982-03-15
申请人： James Jennings
发明人： James Jennings
摘要： There is shown and described a new and unique counter mechanism or circuit which includes feedback latches, in cascade, and which monitors a "carry-in" signal which selectively causes the latch to toggle. When the contents of the latch is a binary 1, the carry-in signal propagates through the counter as a "carry-out" signal. Counting by the circuit occurs when the count input and carry-in signals are active.
摘要翻译： 显示和描述了一种新颖且独特的计数器机构或电路，其包括级联的反馈锁存器，并且其监视选择性地使闩锁切换的“进位”信号。 当锁存器的内容是二进制1时，进位信号作为“进位输出”信号通过计数器传播。 当计数输入和进位信号有效时，会发生电路计数。
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