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公开(公告)号：US20250068497A1
公开(公告)日：2025-02-27
申请号：US18948491
申请日：2024-11-15
Applicant: UPBEAT TECHNOLOGY Co., Ltd
Inventor： Chung-Chieh CHEN , Da-Ming CHIANG , Shuo-Hong HUNG , Bing-Chen WU
Abstract: An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.
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公开(公告)号：US12237835B2
公开(公告)日：2025-02-25
申请号：US17667027
申请日：2022-02-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Robert Mark Englekirk
IPC: H03K3/037 , G06F1/26 , H03K17/082 , H04L12/10
Abstract: Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments preform the following functions: detecting the initial phase of device startup; determining which of pins A and B is coupled to an I/O line (and thus is the I/O pin), and which is coupled to the storage capacitor (and thus is the CAP pin); and generating a flag signal indicating that determination to other circuitry within the peripheral. Detection of pin characteristics is determined at device startup by latching the fastest rising signal on pins A and B, flagging that signal line as being the I/O line, and preventing further changes to the latch output until the next startup cycle.
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公开(公告)号：US20250060767A1
公开(公告)日：2025-02-20
申请号：US18722051
申请日：2022-12-02
Applicant: Endress+Hauser Flowtec AG
Inventor： Pascal Buchschacher , Alex Huber , Hanspeter Schmid , Werner Tanner
Abstract: The signal transmission system comprises a transmitter circuit, a receiver circuit and a signal cable. A current divider is formed by a terminating resistor between the signal conductors of the signal cable. The transmitter circuit drives a loop current. When the receiver circuit input voltage has a voltage level above a first switching voltage threshold value, the output voltage assumes a first voltage level. The output voltage maintains the first voltage level when the input voltage is below the first switching voltage threshold value but above a second switching voltage threshold value. The transmitter circuit is configured to modulate the loop current with at least two different non-zero magnitudes at successive times. The first magnitude is greater than a first switching current threshold value and the second magnitude is less than the first switching current threshold value and greater than a second switching current threshold value.
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公开(公告)号：US20250060410A1
公开(公告)日：2025-02-20
申请号：US18937072
申请日：2024-11-05
Inventor： SHANG HSIEN YANG , CHUNG-CHIEH YANG , YUNG-CHOW PENG , CHIH-CHIANG CHANG
IPC: G01R31/319 , G01R31/317 , G01R31/3183 , H03K3/037 , H03K5/26
Abstract: A delay measurement system and a measurement method are provided. The delay measurement system includes a delay control device and a comparator. The delay control device is configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a comparator. The comparator is configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of a third signal delays the second delay time with respect to the rising edge of the first signal, and the third signal is generated by a device under test (DUT) in response to the first signal.
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公开(公告)号：US12231125B1
公开(公告)日：2025-02-18
申请号：US18208753
申请日：2023-06-12
Applicant: SYNOPSYS, INC.
Inventor： Sai Yaswanth Divvela , Amit Verma , Basannagouda Reddy , Deepak D. Sherlekar
Abstract: A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.
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Patent Agency Ranking
公开(公告)号：US12224755B2
公开(公告)日：2025-02-11
申请号：US18489692
申请日：2023-10-18
Inventor： Huaixin Xian , Liu Han , Jing Ding , Qingchao Meng
IPC: H03K5/135 , G06F1/04 , G06F30/392 , H03K3/037 , H03K17/687 , G06F117/04
Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
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公开(公告)号：US20250047287A1
公开(公告)日：2025-02-06
申请号：US18792540
申请日：2024-08-01
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Qiuyan Zu , Gang Yan , Yong Wang , Pengzhan Zhang
Abstract: The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.
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公开(公告)号：US20250047242A1
公开(公告)日：2025-02-06
申请号：US18543269
申请日：2023-12-18
Applicant: NUVOTON TECHNOLOGY CORPORATION
Inventor： Cheng-Tao LI , Ping-Wen LAI
Abstract: An oscillation circuit includes: a current mirror circuit outputting a reference current; a charging and discharging circuit charging a first charge storage element by using one of the reference currents or discharging the first charge storage element, to generate a first control voltage; an output stage circuit including a first switch transistor controlled by the first control voltage to output a first oscillation signal; a first resistor; a second resistor; and a diode circuit. The first resistor and the second resistor have same directional temperature drifts, a first resistance of the first resistor is greater than a second resistance of the second resistor, and a first resistance drift of the first resistor with a temperature variation is smaller than a second resistance drift of the second resistor with the temperature variation, such that the effect of the temperature variation on a frequency accuracy is reduced.
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公开(公告)号：US12218669B2
公开(公告)日：2025-02-04
申请号：US18330731
申请日：2023-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-Ook Jung , Se Keon Kim , Hyunjun Kim , Kyeong Rim Baek , Keonhee Cho
Abstract: A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.
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10.发明授权公开(公告)号：US12210631B1
公开(公告)日：2025-01-28
申请号：US17743797
申请日：2022-05-13
Applicant: Marvell Asia Pte Ltd
Inventor： Eric Hunt-Schroeder , Tian Xia
Abstract: A method for preventing unauthorized access to information in a semiconductor device that is secured with a security protocol that uses a first portion of the information may include in response to a verified inaccessibility-inducing signal, unlocking safety lock circuitry which is operable to prevent unintentional activation of self-destruction in the semiconductor device, and initiating the self-destruction of at least a portion of the semiconductor device. A semiconductor device is configured to prevent unauthorized access to information available therein that is secured with a security protocol that uses a first portion of the information. The semiconductor device may include safety lock circuitry operable to prevent unintentional activation of self-destruction in the semiconductor device and control circuitry operable to unlock the safety lock circuitry and to initiate the self-destruction of at least a portion of the semiconductor device in response to a verified inaccessibility-inducing signal.
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