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公开(公告)号：US20220360253A1
公开(公告)日：2022-11-10
申请号：US17815156
申请日：2022-07-26
发明人： Huaixin XIAN , Qingchao MENG , Yang ZHOU , Shang-Chih HSIEH
IPC分类号： H03K3/037 , H03K3/288 , H03K3/356 , H03K3/3562 , H03K3/289
摘要： A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.
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公开(公告)号：US11177796B2
公开(公告)日：2021-11-16
申请号：US16841593
申请日：2020-04-06
摘要： A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.
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公开(公告)号：US20210313971A1
公开(公告)日：2021-10-07
申请号：US16841593
申请日：2020-04-06
摘要： A flip-flop is provided that includes an input latch, configured to receive a data signal and a complement and produce set and reset pulses based on a clock and a difference between the data signal and the complement; and an output latch, configured to store a data value in a first memory and a complement data value in a second memory based on the set and reset pulses and the clock. Various buffers configured to invert and amplify the set and reset pulses before provision to the output latch stages are optionally disposed between the input and output latches. The input latch includes two signal arms, two difference transistors (one gate controlled by the clock and the other by a clock complement) coupled oppositely to one another (by respective drains and sources) to the signal arms, and two regeneration inverters coupled oppositely to one another to the signal arms.
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公开(公告)号：US20050156643A1
公开(公告)日：2005-07-21
申请号：US11077297
申请日：2005-03-10
申请人： Karl Edwards
发明人： Karl Edwards
CPC分类号： H03K3/012 , H03K3/2825 , H03K3/288
摘要： A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.
摘要翻译： 提供高速，电流驱动的锁存器。 锁存器传导电流并包括输出，SET电路和RESET电路。 输出在第一状态和第二状态之间变化。 SET电路在第一状态下导通锁存器中存在的电流，使得SET电路保持接近将晶体管的输出从第一电平改变到第二电平所需的电平，并且RESET电路在 第二电平使得RESET电路接近将晶体管的输出从第二电平改变到第一电平所需的电平。
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公开(公告)号：US5550412A
公开(公告)日：1996-08-27
申请号：US304537
申请日：1994-09-12
申请人： Douglas L. Anneser
发明人： Douglas L. Anneser
IPC分类号： H03K3/288 , H03K17/66 , H03K17/691 , H01H47/00
CPC分类号： H03K3/288 , H03K17/667 , H03K17/691 , Y10T307/747 , Y10T307/826
摘要： A transformer-based electrical circuit that isolates a low voltage level input control signal from a power switching device, such a MOSFET, is disclosed. The circuit includes a pair of complementary dual bipolar transistor configurations connected to the secondary winding of a pulse transformer. The low voltage input signal is connected to the primary winding of the transformer. A pair of resistor network transistor drivers connect to corresponding bipolar transistors, whose outputs connect to the gate terminal of the MOSFET. The drivers are also connected to the complementary transistor pairs. A resistive feedback network is connected between the gate terminal of the MOSFET and the complimentary transistor pairs. The feedback network latches the selected drive voltage to the gate of the MOSFET, thereby keeping it on or off irrespective of the fact that the pulse transformer may have saturated.
摘要翻译： 公开了一种基于变压器的电路，其将来自功率开关器件（例如MOSFET）的低电压电平输入控制信号隔离。 电路包括连接到脉冲变压器的次级绕组的一对互补双极晶体管配置。 低压输入信号连接到变压器的初级绕组。 一对电阻网络晶体管驱动器连接到相应的双极晶体管，其输出连接到MOSFET的栅极端子。 驱动器也连接到互补晶体管对。 电阻反馈网络连接在MOSFET的栅极端子和互补晶体管对之间。 反馈网络将所选择的驱动电压锁存到MOSFET的栅极，从而保持其导通或截止，而不管脉冲变压器可能具有饱和的事实。
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公开(公告)号：US5107507A
公开(公告)日：1992-04-21
申请号：US198961
申请日：1988-05-26
IPC分类号： G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082
CPC分类号： G06F11/10 , G06F13/4027 , G06F13/4059 , G06F13/4072 , H03K19/0826 , H03K3/288
摘要： A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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公开(公告)号：US4958090A
公开(公告)日：1990-09-18
申请号：US320281
申请日：1989-03-06
申请人： Lars G. Jansson
发明人： Lars G. Jansson
IPC分类号： H03K3/286 , H03K3/288 , H03K19/003 , H03K19/088
CPC分类号： H03K3/288 , H03K19/00307 , H03K19/00353 , H03K19/088
摘要： Dual phase splitter transistor elements, an output phase splitter transistor element and a secondary phase splitter transistor element, are coupled in current mirror configuration in a TTL output buffer circuit. The output phase splitter transistor element is coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements. The collector of the secondary phase splitter transistor element is coupled in a supplemental circuit which can have a variable load without direct connection to the pullup transistor element and output. A low impedance current sourcing active transistor element is coupled in emitter follower configuration at the collector node of the secondary phase splitter transistor element for supplying mirroring current through the emitter of the secondary phase splitter transistor element to reduce current hogging at the dual phase splitter transistor elements. The current sourcing transistor element is coupled in parallel with the supplemental circuit thereby providing a variable current which varies inversely with the collector current supplied by the supplemental circuit. The invention is applied in a JK flip flop circuit as the output buffer circuits with the collector of the secondary phase splitter transistor element coupled to the cross feedback circuit. The cross feedback transistor element in the cross feedback circuit is therefore isolated from the pullup transistor element and output avoiding feedback transistor breakdown when the output is at high potential. The current sourcing transistor element prevents current hogging between the dual phase splitter transistor elements.
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公开(公告)号：US4763016A
公开(公告)日：1988-08-09
申请号：US937879
申请日：1986-12-04
申请人： Davide Chieli
发明人： Davide Chieli
摘要： A circuit device is provided for feedback controlling a transistor to switch off which is incorporated to a transfer circuit as the last stage thereof, and when, during the "off" phase, a current is drawn through its base by another transistor, referred to as the switch-off transistor, which is conductive for just the time required for said switching off to take place.
摘要翻译： 提供电路装置用于反馈控制晶体管关断，其作为其最后阶段结合到传输电路，并且当在“截止”阶段期间，另一个晶体管将电流从其基极吸取，被称为 关断晶体管，其仅在所述关断发生所需的时间内导通。
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公开(公告)号：US4614885A
公开(公告)日：1986-09-30
申请号：US630544
申请日：1984-07-13
CPC分类号： H03K3/288
摘要： A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.
摘要翻译： 具有锁存器的分相器包括形式为电流开关（T1，T2，T3，R3）形式的真互补发生器，其根据输入信号（VIN）提供两个互补输出信号。 这种真互补发生器的输出在每种情况下都连接到相关的射极跟随器（T4，T5）。 两个发射极跟随器（T4，T5）具有相同的发射极电阻（R6，R7），其同时用作两个交叉耦合晶体管（T6，T7）的集电极负载电阻，其也包括相同但较高的发射极电阻（R13，R14） 发射极跟随器（T6，T7）。 交叉耦合晶体管（T6，T7）的发射极各自连接到由电流开关组成的输出级（T8，T9，T11）的两个输入之一。 该电流开关通过时钟控制的过渡器（T11）连接到工作电压（VEE）。 在激励输出级时，即当晶体管（T11）导通时，其中一个交叉耦合晶体管（T6，T7）的有源发射极电阻被拉低到低于发射极电阻（R6，R7）的值 发射极跟随器（T4，T5），从而使闩锁电路根据输入信号被锁存。
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公开(公告)号：US4605871A
公开(公告)日：1986-08-12
申请号：US588476
申请日：1984-03-12
申请人： John E. Price , Larry W. De Clue
发明人： John E. Price , Larry W. De Clue
IPC分类号： H03K3/288 , H03K19/086 , H03K19/013 , H03K19/092 , H03K19/20
CPC分类号： H03K19/0866 , H03K19/086 , H03K3/288
摘要： A bipolar logic gate is provided which will perform logical operations involving the complement of one or more input signals. The gate resembles the conventional ECL OR/NOR gate circuit except that a level shift input transistor is substituted for the standard reference transistor and shifts the voltage level of the input signal whose complement is to be included in the logical operation. A voltage shift of about -0.4 volts occurs either at the base or on the emitter of the level shift input transistor. As a consequence of the voltage shift and subsequent comparison with unshifted voltages, the input voltages are compared with each other rather than with a reference voltage, V.sub.BB. Logically, the complement of the input is included in the OR'd and NOR'd outputs provided on the output lines. The logic gate may be incorporated in combinational and sequential logic circuits.
摘要翻译： 提供双极逻辑门，其将执行涉及一个或多个输入信号的补码的逻辑运算。 门类似于常规的ECL或/或门门电路，除了用电平移位输入晶体管代替标准参考晶体管，并且将逻辑运算中的补码的输入信号的电压电平移位。 在电平移位输入晶体管的基极或发射极处发生约-0.4伏特的电压偏移。 作为电压偏移和随后与未移相电压的比较的结果，将输入电压彼此进行比较，而不是使用参考电压VBB。 在逻辑上，输入的补码包含在输出线上提供的OR'和NOR'输出中。 逻辑门可以并入组合和顺序逻辑电路中。
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