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公开(公告)号：US11766563B2
公开(公告)日：2023-09-26
申请号：US17881589
申请日：2022-08-04
CPC分类号： A61N1/36034 , A61N1/0472 , H01F27/24 , H01F27/2823 , H03K3/353 , H05K1/181 , H01F2027/2833 , H05K2201/1003 , H05K2201/10166 , H05K2201/10545
摘要： Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.
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公开(公告)号：US20220345119A1
公开(公告)日：2022-10-27
申请号：US17729844
申请日：2022-04-26
发明人： Harald Garvik
摘要： A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.
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公开(公告)号：US20220294426A1
公开(公告)日：2022-09-15
申请号：US17828161
申请日：2022-05-31
发明人： Manikandan R R
摘要： In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.
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公开(公告)号：US11201606B2
公开(公告)日：2021-12-14
申请号：US16878643
申请日：2020-05-20
发明人： Qingyun Di , Qihui Zhen , Quanmin Yang
IPC分类号： H03K3/353
摘要： The present invention discloses a CSAMT transmitter, including: a first transmitter, where the first transmitter includes a first generator, a first rectifier module, a first transmission module, and a second transmission module, the first generator is connected to the first transmission module and the second transmission module by using the first rectifier module; and a second transmitter, where the second transmitter includes a second generator, a second rectifier module, a third transmission module, and a fourth transmission module, the second generator is connected to the third transmission module and the fourth transmission module by using the second rectifier module, where the first transmission module is connected to the third transmission module, and the second transmission module is connected to the fourth transmission module; the first transmission module has the same voltage as the third transmission module, and the second transmission module has the same voltage as the fourth transmission module.
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公开(公告)号：US20210020629A1
公开(公告)日：2021-01-21
申请号：US16575407
申请日：2019-09-19
发明人： Chun-Sheng Chen
IPC分类号： H01L27/085 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/10 , H03K3/353 , H03K19/20 , G11C11/412
摘要： A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.
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公开(公告)号：US10812090B2
公开(公告)日：2020-10-20
申请号：US16681469
申请日：2019-11-12
摘要： In an embodiment, a clock generator has a variable-modulus frequency divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus-control signal generated by a temperature-compensation circuit. A jitter filter is coupled to the output of the variable-modulus frequency divider and to the temperature-compensation circuit and generates a compensated clock signal having switching edges that are delayed, with respect to the divided clock signal, by a time correlated to a quantization-error signal.
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公开(公告)号：US20200169262A1
公开(公告)日：2020-05-28
申请号：US16681469
申请日：2019-11-12
摘要： In an embodiment, a clock generator has a variable-modulus frequency divider that receives a high-frequency clock signal and outputs a divided clock signal having a frequency controlled by a modulus-control signal generated by a temperature-compensation circuit. A jitter filter is coupled to the output of the variable-modulus frequency divider and to the temperature-compensation circuit and generates a compensated clock signal having switching edges that are delayed, with respect to the divided clock signal, by a time correlated to a quantization-error signal.
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公开(公告)号：US20200162063A1
公开(公告)日：2020-05-21
申请号：US16748417
申请日：2020-01-21
申请人： SK hynix Inc.
发明人： Jeong-Eun SONG
摘要： Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.
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公开(公告)号：US10256811B2
公开(公告)日：2019-04-09
申请号：US15654792
申请日：2017-07-20
发明人： Woojin Chang , Jong-Won Lim , Dong Min Kang , Dong-Young Kim , Seong-il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Min Jeong Shin , Hokyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jongmin Lee , Sungjae Chang , Yoo Jin Jang , Hyunwook Jung , Kyu Jun Cho , Hong Gu Ji
IPC分类号： H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353 , H03K17/0812 , H03K17/10 , H03K17/12 , H03K17/14 , H03K17/16 , H03K17/28
摘要： Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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公开(公告)号：US20170346468A1
公开(公告)日：2017-11-30
申请号：US15600427
申请日：2017-05-19
发明人： YUKIO OKAZAKI , KAZUTOSHI SATOU , NORIAKI SAITO
CPC分类号： H03K3/014 , G01S7/023 , G01S7/032 , G01S7/28 , G01S13/288 , G01S13/88 , G01S13/931 , G06F1/04 , G06F1/3203 , H03K3/353
摘要： A radar apparatus includes a transmitter including a plurality of circuits that intermittently transmit one or more radar signals, the plurality of circuits being suspended power supplying during a period in which the one or more radar signals are not transmitted, variation detection circuitry that detects process variations of the plurality of circuits, and determination circuitry that determines a startup timing of each of the plurality of circuits in response to the process variations and outputs startup commands in response to the determined startup timings to the plurality of circuits.
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