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公开(公告)号：US12040801B2
公开(公告)日：2024-07-16
申请号：US17976096
申请日：2022-10-28
申请人： SK hynix Inc.
发明人： Hong Ki Moon
摘要： A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.
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公开(公告)号：US12019912B2
公开(公告)日：2024-06-25
申请号：US17316942
申请日：2021-05-11
发明人： Keith A. Benjamin
IPC分类号： G06F3/06 , G06F7/58 , G11C11/409 , H03K3/84
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F7/584 , H03K3/84 , G11C11/409
摘要： An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.
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3.发明公开公开(公告)号：US20240171411A1
公开(公告)日：2024-05-23
申请号：US17788523
申请日：2021-08-31
发明人： Xiangye Wei
CPC分类号： H04L9/3278 , H03K3/0315 , H03K3/84
摘要： Provided are a physical unclonable function device and an operation method thereof, and an electronic device. The device includes: a first signal generating circuit configured to generate a first clock signal of n-th period according to a control signal of the n-th period and an input signal of the n-th period; a second signal generating circuit configured to generate a second clock signal of the n-th period according to the control signal of the n-th period and the input signal of the n-th period; an output circuit configured to output an output signal of the n-th period according to the first and second clock signal of the n-th period; and a control circuit configured to process an initial control signal of the n-th period to obtain the control signal of the n-th period according to a reference value comprising a logic level of an output signal of (n−1)-th period.
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公开(公告)号：US20240128957A1
公开(公告)日：2024-04-18
申请号：US18483251
申请日：2023-10-09
CPC分类号： H03K3/84 , H03K5/134 , H03K2005/00273
摘要： The present description concerns a random number generation circuit (2) of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO1, R02) implemented in CMOS-on-FDSOI technology; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other one of the two oscillators (R02) and delivering a corresponding binary signal (Beat); and a circuit (200) controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, R02) based on a period difference between the two oscillators (RO1, R02).
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5.发明授权公开(公告)号：US11962305B2
公开(公告)日：2024-04-16
申请号：US17303839
申请日：2021-06-09
申请人： NXP B.V.
发明人： Björn Fay
CPC分类号： H03K3/84 , G06F7/58 , G06F7/588 , H03K3/0315 , H03K21/08
摘要： A true random number generator circuit includes a ring oscillator and a plurality of sampling circuits. The ring oscillator includes a plurality of series-connected stages coupled together in a ring. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. A sampling circuit of the plurality of sampling circuits has an input coupled to a node located between two adjacent stages of the plurality of series-connected stages. Every node of the ring oscillator is coupled to a corresponding sampling circuit of the plurality of sampling circuits. In another embodiment, a method for generating a random number is provided.
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公开(公告)号：US11870444B1
公开(公告)日：2024-01-09
申请号：US18097502
申请日：2023-01-17
发明人： Chun-Heng You , Kai-Hsin Chuang , Chi-Yi Shao
CPC分类号： H03K3/84 , G04F10/005 , H03K3/037 , H03K19/21
摘要： An entropy source circuit is provided. The entropy source circuit includes a digital circuit, a determination circuit and a time-to-digital converter (TDC), wherein the determination circuit is coupled to the digital circuit, and the TDC is coupled to the determination circuit. The digital circuit is configured to generate result data at a second time point according to input data received at a first time point, and the determination circuit is configured to perform determination on reference data with dynamic output generated by the digital circuit, to generate a determination result, wherein the reference data is equal to the result data. In addition, the TDC is configured to perform a time-to-digital conversion on a delay of the digital circuit for generating the result data according to the input data with aid of the determination signal, in order to generate entropy data corresponding to the delay.
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公开(公告)号：US11742836B1
公开(公告)日：2023-08-29
申请号：US17659211
申请日：2022-04-14
发明人： Kangguo Cheng , Carl Radens
摘要： The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.
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公开(公告)号：US20230076714A1
公开(公告)日：2023-03-09
申请号：US17899802
申请日：2022-08-31
发明人： Benny SHATIT , Ming-Che HUNG , Tsung-Hsueh LI
摘要： An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.
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公开(公告)号：US20220247395A1
公开(公告)日：2022-08-04
申请号：US17166012
申请日：2021-02-03
发明人： Moshe Alon
摘要： An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.
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公开(公告)号：US11366640B2
公开(公告)日：2022-06-21
申请号：US16637351
申请日：2018-08-07
发明人： Krzysztof Golofit , Piotr Wieczorek
摘要： Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS′), which have outputs (o-GPRS, o-GPRS′) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US′, i-US′) of a control circuit (US′), having output (o-US′) connected to control inputs (s-GPRS, s-GPRS′) of the adjustable speed ring oscillators (GPRS, GPRS′). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).
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