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公开(公告)号：US12199610B2
公开(公告)日：2025-01-14
申请号：US18531639
申请日：2023-12-06
Applicant: Renesas Electronics America Inc.
Inventor： Dong-Young Chang , Steven Ernest Finn
IPC: H03K3/017 , H03K5/156 , H03K7/08 , H03K17/687
Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.
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公开(公告)号：USRE50213E1
公开(公告)日：2024-11-19
申请号：US17833906
申请日：2022-06-07
Applicant: Novatek Microelectronics Corp.
Inventor： Chung-Wen Wu , Wen-Chi Lin , Sih-Ting Wang
IPC: H03K7/08 , G02F1/13357 , G09G3/34
Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.
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公开(公告)号：US12143127B2
公开(公告)日：2024-11-12
申请号：US18166644
申请日：2023-02-09
Applicant: Infineon Technologies AG
Inventor： Dirk Hammerschmidt
Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.
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公开(公告)号：US12113534B2
公开(公告)日：2024-10-08
申请号：US18193078
申请日：2023-03-30
Applicant: Kwang Hee Kim
Inventor： Kwang Hee Kim
CPC classification number: H03K3/017 , H03K3/313 , H03K3/356034 , H03K7/08
Abstract: Provided are a device for adjusting an ultrasonic resonance frequency and a method of controlling the same. A device according to an embodiment of the present disclosure includes a circuit board configured to determine and output a resonance frequency. In addition, the device includes a frequency adjustor connected to at least one of a plurality of circuits mounted on the circuit board.
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公开(公告)号：US20240333139A1
公开(公告)日：2024-10-03
申请号：US18128972
申请日：2023-03-30
Inventor： Shengyuan LI , Leon Samuel WANG , I-Ning KU , Xicheng JIANG
Abstract: An apparatus includes a circuitry to perform a first startup stage and to vary, during a second startup stage subsequent to the first startup stage, a duty cycle of a pulse controlling one or more switches of the circuitry.
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公开(公告)号：US20240314005A1
公开(公告)日：2024-09-19
申请号：US18592793
申请日：2024-03-01
Applicant: NEC Corporation
Inventor： Masaaki TANIO
CPC classification number: H04L25/4902 , H03K4/026 , H03K7/08
Abstract: A signal modulation apparatus includes: a reference signal generator that generates an analog reference signal by removing at least one harmonic signal component corresponding to at least one higher-order frequency from a triangular wave signal; a modulation signal generator that performs pulse width modulation for comparing the analog reference signal with an analog input signal, thereby to generate an analog modulation signal; a digital signal converter that converts the analog modulation signal to a digital output signal; and a nonlinear converter that performs nonlinear conversion corresponding to waveform conversion for converting the triangular wave signal to the analog reference signal, on the digital output signal or the analog input signal.
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公开(公告)号：US20240213962A1
公开(公告)日：2024-06-27
申请号：US18541152
申请日：2023-12-15
Applicant: Canon Kabushiki Kaisha
Inventor： ICHIRO IIJIMA , HIROTAKA ITTOGI
CPC classification number: H03K3/017 , H03K7/08 , H04L7/0087
Abstract: In a data carrier apparatus, a first determination unit determines a duty ratio of each pulse of a pulse signal received from a data carrier driving apparatus, and a second determination unit determines a frequency of each pulse of the received pulse signal. A calibration unit performs calibration of a reference value to be used for determination performed by the second determination unit, during a calibration period. A demodulation unit demodulates data conveyed by the received pulse signal. The demodulation unit performs first demodulation based on a determination result of the first determination unit during the calibration period, and start second demodulation based on the determination result of the first determination unit and a determination result of the second determination unit when the calibration period ends.
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公开(公告)号：US20240195400A1
公开(公告)日：2024-06-13
申请号：US18454507
申请日：2023-08-23
Inventor： Min-Hyung CHO , Yi-Gyeong KIM , Su-Jin PARK , Young-Deuk JEON
CPC classification number: H03K7/08 , H03K5/05 , H03K5/131 , H03K5/15066
Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
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公开(公告)号：US11996962B2
公开(公告)日：2024-05-28
申请号：US17768979
申请日：2020-10-16
Applicant: Rohm Co., Ltd.
Inventor： Shinya Masuda , Satoshi Tanaka , Toru Mukai , Hiroki Yamakami
CPC classification number: H04L25/49 , H03K7/08 , H04B14/026 , H04B14/046 , H04L25/03
Abstract: A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n−1)/2f, where f is the frequency of EMI noise.
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公开(公告)号：US20240128859A1
公开(公告)日：2024-04-18
申请号：US18046966
申请日：2022-10-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Huihuang CHEN
CPC classification number: H02M1/4208 , H03K7/08
Abstract: A pulse width modulation (PWM) system includes a PWM circuit and a controller. The PWM circuit includes a counter, a period register, and a duty cycle register. The controller is coupled to the PWM circuit. The controller is configured to calculate a period value and a duty cycle value. The controller is also configured to load the duty cycle value into the duty cycle register responsive to a count value of the counter being equal to a value of the duty cycle register and the duty cycle value being less than the period value.
