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公开(公告)号：US20230006677A1
公开(公告)日：2023-01-05
申请号：US17942077
申请日：2022-09-09
申请人： Marc Loinaz
发明人： Marc Loinaz
摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.
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公开(公告)号：US11249509B2
公开(公告)日：2022-02-15
申请号：US16993231
申请日：2020-08-13
申请人： AMBIQ MICRO, INC.
发明人： Scott Hanson
IPC分类号： H03L7/18 , G06F1/06 , H03L7/06 , H03L7/181 , G06F1/3237 , G06F1/3287 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G05F1/575 , G06F1/3296 , H02M3/158 , H02M1/00
摘要： An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
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公开(公告)号：US20220038103A1
公开(公告)日：2022-02-03
申请号：US17391544
申请日：2021-08-02
发明人： Stuart D. Sandberg
摘要： In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.
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4.发明授权公开(公告)号：US11218155B2
公开(公告)日：2022-01-04
申请号：US17101665
申请日：2020-11-23
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi , Matthew Mikkelsen
摘要： Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
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公开(公告)号：US11212071B2
公开(公告)日：2021-12-28
申请号：US16595654
申请日：2019-10-08
申请人： DENSO CORPORATION
发明人： Nobuaki Matsudaira
IPC分类号： H04L7/033 , H04L29/06 , H03L7/00 , H04B1/10 , H04B3/06 , H04L7/00 , H04L12/40 , H04L25/03 , H04L7/10 , H03L7/06
摘要： A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.
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公开(公告)号：US11206051B2
公开(公告)日：2021-12-21
申请号：US16896557
申请日：2020-06-09
摘要： A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.
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公开(公告)号：US11199621B2
公开(公告)日：2021-12-14
申请号：US16278006
申请日：2019-02-15
申请人： NXP B.V.
摘要： In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: a frequency detector configured to monitor an output frequency of a clock-stop sensor of said transponder, wherein said frequency detector is further configured to determine if said output frequency falls within a response detection frequency range of an external reader, and a frequency shifter configured to shift, in response to the frequency detector determining that the output frequency falls within said response detection frequency range, said output frequency to a value outside said response detection frequency range. In accordance with a second aspect of the present disclosure, a corresponding method of operating a transponder is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.
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公开(公告)号：US11048284B2
公开(公告)日：2021-06-29
申请号：US16566368
申请日：2019-09-10
申请人： Intel Corporation
IPC分类号： G05F1/625 , G01R19/165 , H03K5/24 , H03L7/093 , H03L7/06
摘要： Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US11025261B2
公开(公告)日：2021-06-01
申请号：US16894607
申请日：2020-06-05
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US10958277B1
公开(公告)日：2021-03-23
申请号：US16562377
申请日：2019-09-05
发明人： Viorel Olariu
摘要： This application is directed to an electronic device including a phase locked loop (PLL) circuit. The PLL includes a voltage-controlled oscillator (VCO) and the PLL is configured to generate a plurality of periodic signals having a first frequency. Optionally, the periodic signals are equally separated in phase to cover an entire period cycle of the first frequency. The electronic device includes a first multiplexer coupled to the PLL, the first multiplexer being external to the PLL. The first multiplexer configured to receive a first selection signal, select a first periodic signal of the plurality of periodic signals based on the first selection signal, and provide the first selected periodic signal to a first clock-driven circuit that is distinct from the PLL. The electronic device further includes a controller circuit coupled to the first multiplexer, the controller circuit being configured to provide the first selection signal to the first multiplexer.
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