利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5573 条记录 (耗时 0.027 秒)

    SYSTEM AND METHOD FOR CLOCK RESYNCHRONIZATION
    2.
    发明公开
    SYSTEM AND METHOD FOR CLOCK RESYNCHRONIZATION 审中-公开

    公开(公告)号：US20230336325A1

    公开(公告)日：2023-10-19

    申请号：US17720087

    申请日：2022-04-13

    申请人： STMicroelectronics S.r.l.

    发明人： Francesco Pappalardo ,  Elena Salurso

    IPC分类号： H04L7/033 ,  H03L7/06

    CPC分类号： H04L7/0331 ,  H03L7/06

    摘要： A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

    POSITRON EMISSION TOMOGRAPHY SYSTEM WITH A TIME SYNCHRONIZED NETWORK
    3.
    发明申请
    POSITRON EMISSION TOMOGRAPHY SYSTEM WITH A TIME SYNCHRONIZED NETWORK 有权

    公开(公告)号：US20230006677A1

    公开(公告)日：2023-01-05

    申请号：US17942077

    申请日：2022-09-09

    申请人： Marc Loinaz

    发明人： Marc Loinaz

    IPC分类号： H03L7/06 ,  G01N15/14 ,  G01S7/4865 ,  G01T1/29 ,  G01S17/26 ,  G01S17/88

    摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

    STATE ESTIMATION FOR TIME SYNCHRONIZATION
    5.
    发明申请
    STATE ESTIMATION FOR TIME SYNCHRONIZATION 有权

    公开(公告)号：US20220038103A1

    公开(公告)日：2022-02-03

    申请号：US17391544

    申请日：2021-08-02

    申请人： CommScope Technologies LLC

    发明人： Stuart D. Sandberg

    IPC分类号： H03L7/06 ,  H04L7/033 ,  H04J3/06 ,  H03M1/06

    摘要： In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

    Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter
    6.
    发明授权
    Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter 有权

    公开(公告)号：US11218155B2

    公开(公告)日：2022-01-04

    申请号：US17101665

    申请日：2020-11-23

    申请人： Ciena Corporation

    发明人： Tingjun Wen ,  Sadok Aouini ,  Naim Ben-Hamida ,  Mahdi Parvizi ,  Matthew Mikkelsen

    IPC分类号： H03L7/06 ,  H03L7/197 ,  H03L7/087 ,  H03L7/107 ,  H03L7/093 ,  H03L7/099

    摘要： Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

    Receiver
    7.
    发明授权
    Receiver 有权

    公开(公告)号：US11212071B2

    公开(公告)日：2021-12-28

    申请号：US16595654

    申请日：2019-10-08

    申请人： DENSO CORPORATION

    发明人： Nobuaki Matsudaira

    IPC分类号： H04L7/033 ,  H04L29/06 ,  H03L7/00 ,  H04B1/10 ,  H04B3/06 ,  H04L7/00 ,  H04L12/40 ,  H04L25/03 ,  H04L7/10 ,  H03L7/06

    摘要： A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

    Digital offset frequency generator based radio frequency transmitter
    8.
    发明授权
    Digital offset frequency generator based radio frequency transmitter 有权

    公开(公告)号：US11206051B2

    公开(公告)日：2021-12-21

    申请号：US16896557

    申请日：2020-06-09

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Debapriya Sahu ,  Srinivas Venkata Veeramreddi ,  Raghu Ganesan

    IPC分类号： H04B1/16 ,  H03F3/19 ,  H03F3/21 ,  H03L7/06 ,  H03K19/21 ,  H03L7/099 ,  H04B1/04

    摘要： A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.

    Clock-stop frequency adjustment for a transponder
    9.
    发明授权
    Clock-stop frequency adjustment for a transponder 有权

    公开(公告)号：US11199621B2

    公开(公告)日：2021-12-14

    申请号：US16278006

    申请日：2019-02-15

    申请人： NXP B.V.

    发明人： Shankar Joshi ,  Raghavendra Kongari ,  Björn Rasmussen

    IPC分类号： G01S13/76 ,  G06K19/07 ,  H03L7/06 ,  G06F1/10 ,  H03K7/08 ,  G06K7/00

    摘要： In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: a frequency detector configured to monitor an output frequency of a clock-stop sensor of said transponder, wherein said frequency detector is further configured to determine if said output frequency falls within a response detection frequency range of an external reader, and a frequency shifter configured to shift, in response to the frequency detector determining that the output frequency falls within said response detection frequency range, said output frequency to a value outside said response detection frequency range. In accordance with a second aspect of the present disclosure, a corresponding method of operating a transponder is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.