-
公开(公告)号：US20230125872A1
公开(公告)日：2023-04-27
申请号：US17881417
申请日：2022-08-04
发明人： Seon-Ho HAN , Young-Su KWON
摘要： Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.
-
公开(公告)号：US11637557B2
公开(公告)日：2023-04-25
申请号：US17670540
申请日：2022-02-14
发明人： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
摘要： In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
-
公开(公告)号：US20230122734A1
公开(公告)日：2023-04-20
申请号：US17906984
申请日：2021-03-24
发明人： Xinjian CHEN , Yuanjun LIANG
摘要： Disclosed are a clock and data recovery circuit, method and apparatus. The circuit comprises a receiving module for receiving an analog signal; a first equalization module connected to the receiving module, the first equalization module comprising a first totalizer and a second totalizer; a first sampling module connected to an output end of the first totalizer, the first sampling module comprising a first edge sampler and a second edge sampler that are connected to the output end of the first totalizer, respectively; a second sampling module connected to an output end of the second totalizer; a data processing module connected to both the first sampling module and the second sampling module; a clock recovery module connected to the data processing module; and an output module connected to the clock recovery module. In the present application, by means of the manner, a phase can be adjusted using a bias voltage, thereby accurately recovering clock information.
-
公开(公告)号：US20230118223A1
公开(公告)日：2023-04-20
申请号：US18062591
申请日：2022-12-07
IPC分类号： H03L7/08 , H03L7/00 , G01R31/317 , G04F10/00
摘要： A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
-
公开(公告)号：US20230081578A1
公开(公告)日：2023-03-16
申请号：US17890817
申请日：2022-08-18
发明人： Jerzy A. Teterwak
摘要： A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
-
公开(公告)号：US20230053619A1
公开(公告)日：2023-02-23
申请号：US17819972
申请日：2022-08-16
发明人： Jan Bollenbeck
摘要： Techniques are disclosed for transferring at least one speech signal of a patient during a magnetic resonance imaging examination, wherein the speech signal is recorded by a speech recording device of a wireless communication device assigned to the patient and transmitted at least as part of a communication signal to a receive device of the magnetic resonance imaging device. The communication signal is a modulated signal or is generated from a modulated signal, and to generate the modulated signal the speech signal is modulated onto a carrier signal. The modulated signal is generated by way of a modulation with reduction of the level of the carrier signal.
-
公开(公告)号：US20230035951A1
公开(公告)日：2023-02-02
申请号：US17867795
申请日：2022-07-19
发明人： Yan Ye , Cheng Liang
摘要： A method for controlling a phase-locked loop circuit, can include: acquiring values of a voltage-controlled oscillator capacitor array control signal respectively corresponding to desired values of a frequency control word signal and acquiring values of a charge pump current control signal respectively corresponding to the desired values of the frequency control word signal in a calibration mode, where the frequency control word signal characterizes a ratio of a desired locked frequency to a frequency of a reference signal; and determining a target value of the voltage-controlled oscillator capacitor array control signal corresponding to a target value of the frequency control word signal and a target value of the charge pump current control signal corresponding to the target value of the frequency control word signal in a phase-locked mode, in order to control the phase-locked loop circuit to achieve phase lock.
-
公开(公告)号：US11569814B1
公开(公告)日：2023-01-31
申请号：US17503073
申请日：2021-10-15
申请人： Analog Bits, Inc.
IPC分类号： H03B5/00 , H03B5/12 , H03L7/00 , H03K17/687 , H03L7/08
摘要： A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.
-
公开(公告)号：US20230021026A1
公开(公告)日：2023-01-19
申请号：US17786710
申请日：2019-12-18
发明人： Jeong-Geun KIM , Dong-Hyun BAEK , Jeong-Soo PARK , Ayush BHATTA , Keshab PANDEY , Ganesh MAINALI
摘要： An FMCW radar transmission and reception apparatus radiates, via a transmission antenna, a beat frequency signal of a frequency modulation continuous wave (FMCW) and then receives, via a reception antenna, a reflected signal obtained from the radiated frequency modulation continuous wave (FMCW) signal that is reflected by a target and returns, wherein the frequency of a beat signal of a frequency modulation continuous wave (FMCW) radar can be effectively adjusted by configuring a plurality of phase locked loops (PLLs) used in a transmitter and a receiver, and using the same reference oscillation signal for the plurality of PLLs.
-
公开(公告)号：US11536587B2
公开(公告)日：2022-12-27
申请号：US17213613
申请日：2021-03-26
发明人： Eric Sachse , Gael Close
摘要： A position sensor device includes position sensor elements for generating analog sense signals. A digitization circuit is provided for a digital signal representative of the input phase based on the analog sense signals and a digital processing unit. An output signal is indicative of the position based on the first output of the processing unit. The processing unit comprises an error signal generator for computing an error signal indicative of a phase difference between the digital signal and a feedback signal. A digital filter filters the error signal to generate the first output. A feedback path provides the feedback signal based on the first output and a filter selector to select a filter to be applied from different filters. At least one input on which a common filter circuit operates is scaled differently for each of the different filters to select different filter bandwidths.
-
-
-
-
-
-
-
-
-
搜索结果
3412 条记录 (耗时 0.05 秒)