公开(公告)号：US20240364350A1

公开(公告)日：2024-10-31

申请号：US18767995

申请日：2024-07-10

申请人： SHENZHEN PANGO MICROSYSTEMS CO.,LTD

发明人： KEYONG LIU ,  XIEQUN LIN ,  ZHENYUAN WANG

IPC分类号： H03L7/081 ,  G11C7/22

CPC分类号： H03L7/0814 ,  G11C7/222 ,  H03L7/0818

摘要： This application discloses a programmable circuit, an integrated circuit, and an electronic device. The programmable circuit comprising: a signal conversion module that converts parallel signal input from an external circuit into a serial signal; a signal configuration module that shifts the phase of the serial signal output by the signal conversion module by 0 degree or 360 degree; a first enable signal generation module that generates a first enable signal; a DDR configuration module that generates a second enable signal and sets the DDR mode of the programmable circuit; a phase monitoring module that monitors the phase of the DQS signal input from the external circuit and outputs the monitoring results; a phase adjustment module that adjusts the phase of the first enable signal generated by the first enable signal generation module based on the monitoring results input from the external circuit.

公开(公告)号：US20240356556A1

公开(公告)日：2024-10-24

申请号：US18304332

申请日：2023-04-20

申请人： HIMAX TECHNOLOGIES LIMITED

发明人： Te Chieh Kung

IPC分类号： H03L7/08 ,  H03L7/081 ,  H03L7/089

CPC分类号： H03L7/0807 ,  H03L7/0812 ,  H03L7/0891

摘要： A clock data recovery circuit is provided. The clock data recovery circuit includes a charge pump circuit, a voltage controlled delay line circuit, a charge pump current generator, a phase-frequency detector and a frequency detector. The charge pump circuit generates a control voltage according to a first control signal, a second control signal and a charge pump current. The voltage controlled delay line circuit generates a data clock signal according to the control voltage and a reference clock signal. The charge pump current generator generates the charge pump current to the charge pump circuit according to the control voltage. The phase-frequency detector generates the first control signal according to a feedback clock signal and the reference clock signal. The frequency detector generates the second control signal according to the feedback clock signal and the reference clock signal.

公开(公告)号：US20240313788A1

公开(公告)日：2024-09-19

申请号：US18120838

申请日：2023-03-13

申请人： Apple Inc.

发明人： Karim M. Megawer ,  Jongmin Park ,  Thomas Mayer

IPC分类号： H03L7/083 ,  H03K5/156 ,  H03L7/081

CPC分类号： H03L7/083 ,  H03K5/1565 ,  H03L7/0818

摘要： To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

公开(公告)号：US20240313786A1

公开(公告)日：2024-09-19

申请号：US18678824

申请日：2024-05-30

申请人： Texas Instruments Incorporated

发明人： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC分类号： H03L7/081 ,  H03L7/085

CPC分类号： H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

摘要： An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

公开(公告)号：US20240313785A1

公开(公告)日：2024-09-19

申请号：US18582790

申请日：2024-02-21

申请人： NXP B.V.

发明人： Thomas Baier ,  Jan van Sinderen ,  Jens Fleischhacker

IPC分类号： H03L7/081

CPC分类号： H03L7/0814 ,  H03L7/0818

摘要： Embodiments of a multiphase clock generation device may include an input for feeding a reference clock, a clock generation unit adapted to generate phase-shifted clock signals from the reference clock, and a phase comparator unit functionally coupled with the clock generation unit. The phase comparator unit is adapted to measure a phase shift of the phase-shifted clock signals. The multiphase clock generation device includes a self-calibration unit that is functionally coupled with the clock generation unit. The calibration unit outputs a delay-calibration parameter to the clock generation unit. The clock generation unit is adapted to generate a multiphase clock signal out of the reference clock and the delay-calibration parameter.

公开(公告)号：US20240307546A1

公开(公告)日：2024-09-19

申请号：US18653655

申请日：2024-05-02

申请人： AVILAR THERAPEUTICS, INC.

发明人： Mark George Saulnier ,  Jesse Jingyang Chen ,  Srinivasa Karra ,  Kevin Tyler Sprott ,  Jason Allan Wiles ,  Soumya Ray

IPC分类号： A61K47/54 ,  A61K47/62 ,  C07H5/06 ,  C07H7/02 ,  C07H9/02 ,  C07H9/04 ,  C07H15/203 ,  C07H17/00 ,  C07H17/02 ,  C07H19/02 ,  C07H19/044 ,  H03L7/081 ,  H03L7/099

CPC分类号： A61K47/549 ,  A61K47/62 ,  C07H5/06 ,  C07H7/02 ,  C07H9/02 ,  C07H9/04 ,  C07H15/203 ,  C07H17/00 ,  C07H17/02 ,  C07H19/02 ,  C07H19/044 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0998

摘要： Compounds and compositions that have an asialoglycoprotein receptor (ASGPR) binding ligand bound to an extracellular protein binding ligand for the selective degradation of the target extracellular protein in vivo to treat disorders mediated by the extracellular protein are described.

公开(公告)号：US12092767B2

公开(公告)日：2024-09-17

申请号：US18299039

申请日：2023-04-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin Yin ,  Shang-Fu Yeh ,  Calvin Yi-Ping Chao ,  Chih-Lin Lee ,  Meng-Hsiu Wu

IPC分类号： G01S7/48 ,  G01S7/4861 ,  G01S7/4865 ,  G01S17/10 ,  G04F10/00 ,  H03L7/081 ,  H03L7/089

CPC分类号： G01S7/4861 ,  G01S7/4865 ,  G01S17/10 ,  G04F10/005 ,  H03L7/0812 ,  H03L7/0891

摘要： A method of a sensing device, comprising steps of emitting, by a light source of the sensing device, a light pulse in each of n cycles; measuring, by a single photon avalanche diodes array of the sensing device, a time-of-flight value with a resolution of m in each of the n cycles to generate n raw data frames based on a reflected light of the light pulse; performing, by a pre-processing circuit of the sensing device, a pre-processing operation to n raw data frames to generate k pre-processed data frames, wherein m, n and k are natural numbers, and k is smaller than n; and generating, by post-processor of the sensing device, a histogram according to the k pre-processed data frames and analyzing the histogram to output a depth result.

公开(公告)号：US12047083B2

公开(公告)日：2024-07-23

申请号：US17519490

申请日：2021-11-04

申请人： Arm Limited

发明人： El Mehdi Boujamaa ,  Benoit Labbe ,  David Michael Bull

IPC分类号： H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/081

CPC分类号： H03L7/091 ,  G06F1/08 ,  G06F1/12 ,  H03L7/0814

摘要： In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

公开(公告)号：US12032340B2

公开(公告)日：2024-07-09

申请号：US18236222

申请日：2023-08-21

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Mohammed Abdulaziz ,  Henrik Sjöland ,  Tony Påhlsson

IPC分类号： G04F10/00 ,  H03L7/081 ,  H03L7/183

CPC分类号： G04F10/005 ,  H03L7/0818 ,  H03L7/183

摘要： A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner is configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the TDCs.

公开(公告)号：US12014766B2

公开(公告)日：2024-06-18

申请号：US17846213

申请日：2022-06-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shu-Wei Yang

IPC分类号： G11C11/4076 ,  G06F1/10 ,  H03L7/081

CPC分类号： G11C11/4076 ,  G06F1/10 ,  H03L7/0816

摘要： A system and a method for determining a target locking time for a delay locked loop of a memory apparatus are provided. The system includes a signal generating device, a measuring device and a computing device. The signal generating device is configured to provide a first set of input signals to the memory apparatus in accordance with a first set of first operational parameters and a set of second operational parameters. The measuring device is configured to measure a first set of output signals from the memory apparatus in response to the first set of input signals, and to determine whether the delay locked loop fails at any combination of the first set of first operational parameters and the set of second operational parameters. The computing device is configured to determine a first candidate operational parameter to further determine the target locking time based on the first candidate operational parameter.