公开(公告)号：US20230125664A1

公开(公告)日：2023-04-27

申请号：US17930767

申请日：2022-09-09

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tetsuro ITAKURA ,  Ryunosuke GANDO ,  Daiki ONO ,  Akihide SAI

IPC分类号： H03L7/099 ,  H03L7/085 ,  G01C19/567

摘要： A phase locked loop has an oscillator that varies a frequency according to a control signal, a resonance element that resonates at a predetermined resonance frequency and output a signal obtained by shifting a phase of an output signal of the oscillator by 90 degrees at the resonance frequency, a phase detector that detects a phase error between an output signal of the resonance element and an output signal of the oscillator, a feedback controller that controls a frequency of an output signal of the oscillator by proportional control and integral control according to the phase error, and a control signal corrector that corrects the control signal by adding a correction term corresponding to environment information to an output signal of the feedback controller.

公开(公告)号：US11619914B2

公开(公告)日：2023-04-04

申请号：US17805070

申请日：2022-06-02

申请人： Allegro MicroSystems, LLC

发明人： Charles Myers ,  Shunming Sun ,  Adam Lee

IPC分类号： G04F10/00 ,  H03L7/081 ,  H03L7/085 ,  G01S7/4865

摘要： Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.

公开(公告)号：US20230028270A1

公开(公告)日：2023-01-26

申请号：US17869784

申请日：2022-07-20

申请人： Realtek Semiconductor Corp.

发明人： Yu-Che Yang

IPC分类号： H03L7/099 ,  H03L7/107 ,  H03L7/085

摘要： An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

公开(公告)号：US11555851B2

公开(公告)日：2023-01-17

申请号：US17736904

申请日：2022-05-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mao-Hsuan Chou ,  Ya-Tin Chang ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC分类号： G01R31/317 ,  H03L7/18 ,  H03L7/085

摘要： An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

公开(公告)号：US20230006679A1

公开(公告)日：2023-01-05

申请号：US17931043

申请日：2022-09-09

申请人： STMICROELECTRONICS INTERNATIONAL N.V.

发明人： Prashutosh GUPTA ,  Ankit GUPTA

IPC分类号： H03L7/081 ,  H03L7/085

摘要： An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

公开(公告)号：US11526136B2

公开(公告)日：2022-12-13

申请号：US17443799

申请日：2021-07-27

申请人： Silicon Works Co., Ltd.

发明人： Jong Suk Lee ,  Young Bok Kim ,  Chung Hwan Son ,  Seok Jae Oh ,  Yeh Ju Ka

IPC分类号： G04F10/00 ,  H03L7/085 ,  H03L7/099

摘要： The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.

公开(公告)号：US11502694B1

公开(公告)日：2022-11-15

申请号：US17405188

申请日：2021-08-18

申请人： Nima Badizadegan

发明人： Nima Badizadegan

IPC分类号： H03L7/085 ,  G06F30/34 ,  G06F1/08 ,  H04J3/06

摘要： The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

公开(公告)号：US20220337256A1

公开(公告)日：2022-10-20

申请号：US17849907

申请日：2022-06-27

申请人： Mitsubishi Electric Corporation

发明人： Osamu WADA ,  Hideyuki NAKAMIZO ,  Hiroshi OTSUKA ,  Yukihiro HOMMA

IPC分类号： H03L7/18 ,  H02J50/40 ,  H02J50/20 ,  H03L7/099 ,  H03L7/085 ,  H02J50/70

摘要： In a wireless power transmitting device, a control circuit outputs a control signal for setting a frequency and a phase of an F-PLL signal generated by an F-PLL, the F-PLL generates the F-PLL signal having the frequency and the phase set by the control signal output from the control circuit, and a frequency conversion circuit generates a transmission signal by converting a frequency of the F-PLL signal generated by the F-PLL.

公开(公告)号：US11424750B2

公开(公告)日：2022-08-23

申请号：US16392578

申请日：2019-04-23

申请人： Microsoft Technology Licensing, LLC

发明人： Chuan Pu ,  Wenjun Liao

IPC分类号： H03L7/099 ,  G02B26/08 ,  G02B26/10 ,  H03L7/085

摘要： Techniques are described herein that are capable of adjusting a center frequency of an adaptive voltage controlled oscillator (VCO) that is included in an adaptive phase lock loop (PLL) and/or a phase difference target of the adaptive PLL. An adaptive PLL is a PLL that includes an adaptive VCO. An adaptive VCO is a VCO that is capable of adjusting its center frequency and/or a phase difference target of the adaptive PLL that includes the adaptive VCO. The adaptive PLL may be configured to drive (e.g., control) a device. A drive signal that is used to drive the device and a resulting output signal that is proportional to movement of the device may be fed back to respective inputs of the adaptive PLL so that the phases of those signals may be processed to facilitate adjustment of the center frequency and/or the phase difference target.

公开(公告)号：US11418312B2

公开(公告)日：2022-08-16

申请号：US16578081

申请日：2019-09-20

申请人： Infinera Corporation

发明人： Han H. Sun ,  Kuang-Tsan Wu ,  John D. McNicol

IPC分类号： H04B10/61 ,  H04J14/02 ,  H04L7/00 ,  H04B10/40 ,  H04B10/63 ,  H03L7/085 ,  H03L7/18 ,  H04B10/50 ,  H04J3/06 ,  H04L7/033

摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for clock synchronizing an optical system and multiple leaf systems. In some implementations, a method includes: first data is received from an optical system. The first data is detected using a local oscillator signal provided by a local oscillator laser. The first data is processed using a first sampling rate. A frequency of a clock signal supplied by a reference clock is adjusted based on the processed first data. Second data is transmitted to the optical system at a rate based on the clock signal.