公开(公告)号：US20250007525A1

公开(公告)日：2025-01-02

申请号：US18709161

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO.,LTD

Inventor： Licheng ZHU

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/091

Abstract: A clock synchronization system and method are provided. The clock synchronization system includes: a pulse generation module, configured to receive an input first signal, perform sampling processing of the first signal to obtain a second signal, and generate a pulse signal according to the second signal; a voltage-controlled oscillator, configured to output a first output clock; the output frequency divider module, configured to perform frequency division on the first output clock, and synchronize, according to the pulse signal, the first output clock which has been subjected to the frequency division, so as to obtain a second output clock; and the synchronous output module, configured to receive the first output clock, the second output clock, the first signal, and the pulse signal, and perform synchronization processing on the first signal according to the first output clock, the second output clock and the pulse signal, so as to obtain a third signal.

公开(公告)号：US20240427943A1

公开(公告)日：2024-12-26

申请号：US18749797

申请日：2024-06-21

Applicant: University of Florida Research Foundation, Incorporated

Inventor： Mark Tehranipoor ,  Farimah Farahmandi ,  Kimia Zamiri Azar ,  Md Rafid Muttaki

IPC: G06F21/75 ,  G06F21/76 ,  H03L7/091

Abstract: Various embodiments of the present disclosure provide fault injection attack mitigation for an integrated circuit. In one example, an embodiment provides for providing a sampling clock signal to both high voltage threshold (HVT) cells and low voltage threshold (LVT) cells of a fault-to-time converter sensor of an integrated circuit, providing output of the HVT cells and the LVT cells to an encoder stage of the fault-to-time converter sensor, and detecting one or more fault injection attacks with respect to the integrated circuit based on output of the encoder stage.

公开(公告)号：US12166492B2

公开(公告)日：2024-12-10

申请号：US18336967

申请日：2023-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Ming Fu

IPC: H03L7/081 ,  H03L7/091 ,  H04L7/00 ,  H04L7/033

Abstract: The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method. The method includes: receiving a first reference clock signal and delaying the first reference clock signal as a first clock signal; delaying the first clock signal as a corresponding second clock signal; receiving the corresponding second clock signal from the corresponding first DCDL and generating a corresponding third clock signal via modifying a phase of the corresponding second clock signal; receiving the corresponding third clock signal; receiving a second reference clock signal; and collectively outputting a TDC code combination based on the second reference clock signal and the corresponding third clock signal, wherein the TDC code combination varies in response to a voltage variation of a to-be-monitored voltage.

公开(公告)号：US20240291493A1

公开(公告)日：2024-08-29

申请号：US18581310

申请日：2024-02-19

Applicant: LAPIS Technology Co., Ltd.

Inventor： Atsushi NAGAYAMA

IPC: H03L7/089 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03L7/091 ,  H03L7/099

Abstract: A deadlock detection circuit 20 determines that deadlock occurs, sets a switching signal 106 to H level when a control voltage 104 exceeds an upper limit set in advance, and set the switching signal to L level when the control voltage 104 is lower than a lower limit set in advance. When the switching signal 106 reaches H level, multiplexers 12, 13 perform switching, so that, in place of a reference clock signal 101, an L level signal is input to a phase frequency detector 14, and, in place of a feedback clock signal 107, the reference clock signal 101 is input to the phase frequency detector 14.

公开(公告)号：US12028082B2

公开(公告)日：2024-07-02

申请号：US17966463

申请日：2022-10-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ja Yol Lee

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/091

CPC classification number: H03L7/0993 ,  H03L7/081 ,  H03L7/091

Abstract: A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.

公开(公告)号：US20240213989A1

公开(公告)日：2024-06-27

申请号：US18145867

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Marc Jan Georges TIEBOUT ,  Edwin THALLER ,  Kameran AZADET

IPC: H03L7/091 ,  H03L7/07 ,  H03L7/099

CPC classification number: H03L7/091 ,  H03L7/07 ,  H03L7/0991

Abstract: A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.

公开(公告)号：US11996854B2

公开(公告)日：2024-05-28

申请号：US17895393

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sushrant Monga ,  Vishnu Kalyanamahadevi Gopalan Jawarlal

IPC: H03L7/091 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/091 ,  H03L7/0891 ,  H03L7/099

Abstract: A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.

公开(公告)号：US20240120926A1

公开(公告)日：2024-04-11

申请号：US18482021

申请日：2023-10-06

Applicant: Realtek Semiconductor Corporation

Inventor： Jun YANG

IPC: H03L7/089 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03L7/091 ,  H03L7/0992

Abstract: A charge pump filtering circuit includes a charge pump circuit and a filter circuit. The charge pump circuit includes a first switch and a second switch. The first switch and the second switch are coupled at a first node and are coupled between a power terminal and a ground terminal. The filter circuit includes a first capacitor, a second capacitor, and a first voltage switching circuit. The first capacitor is coupled between the first node and the ground terminal. The second capacitor is coupled between the first voltage switching circuit and the first node.

公开(公告)号：US11955979B2

公开(公告)日：2024-04-09

申请号：US17835292

申请日：2022-06-08

Applicant: Apple Inc.

Inventor： Reetika K Agarwal ,  Abbas Komijani ,  Hongrui Wang

IPC: H03L7/00 ,  H03C3/09 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/197 ,  H04L7/033

CPC classification number: H03L7/0891 ,  H03C3/0941 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/1976 ,  H04L7/033

Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

公开(公告)号：US11929751B1

公开(公告)日：2024-03-12

申请号：US18148652

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankit Garg ,  Abhijit Patki

IPC: H03L7/08 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

CPC classification number: H03L7/0807 ,  H03L7/083 ,  H03L7/091 ,  H03L7/10 ,  H03L7/18

Abstract: A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.