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公开(公告)号：US20240291493A1
公开(公告)日：2024-08-29
申请号：US18581310
申请日：2024-02-19
发明人： Atsushi NAGAYAMA
CPC分类号： H03L7/0891 , H03L7/091 , H03L7/099
摘要： A deadlock detection circuit 20 determines that deadlock occurs, sets a switching signal 106 to H level when a control voltage 104 exceeds an upper limit set in advance, and set the switching signal to L level when the control voltage 104 is lower than a lower limit set in advance. When the switching signal 106 reaches H level, multiplexers 12, 13 perform switching, so that, in place of a reference clock signal 101, an L level signal is input to a phase frequency detector 14, and, in place of a feedback clock signal 107, the reference clock signal 101 is input to the phase frequency detector 14.
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公开(公告)号：US12028082B2
公开(公告)日：2024-07-02
申请号：US17966463
申请日：2022-10-14
发明人： Ja Yol Lee
CPC分类号： H03L7/0993 , H03L7/081 , H03L7/091
摘要： A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.
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公开(公告)号：US20240213989A1
公开(公告)日：2024-06-27
申请号：US18145867
申请日：2022-12-23
申请人： Intel Corporation
CPC分类号： H03L7/091 , H03L7/07 , H03L7/0991
摘要： A system and method for testing or determining a phase noise and/or jitter of a phase locked loop (PLL). The system includes a first PLL configured to generate a first clock signal based on a reference clock signal, a first buffer for providing the reference clock signal to the first PLL, a mixer configured to mix the first clock signal with a second clock signal, an analog-to-digital converter (ADC) configured to convert an output of the mixer to digital data, and a processing circuit configured to process the digital data to determine a phase noise or jitter of the first PLL and generate an output indicative of the phase noise or jitter of the first PLL. The system may include a second PLL configured to generate the second clock signal based on the reference clock signal, and a second buffer for providing the reference clock signal to the second PLL.
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公开(公告)号：US11996854B2
公开(公告)日：2024-05-28
申请号：US17895393
申请日：2022-08-25
CPC分类号： H03L7/091 , H03L7/0891 , H03L7/099
摘要： A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.
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5.发明公开公开(公告)号：US20240120926A1
公开(公告)日：2024-04-11
申请号：US18482021
申请日：2023-10-06
发明人： Jun YANG
CPC分类号： H03L7/0891 , H03L7/091 , H03L7/0992
摘要： A charge pump filtering circuit includes a charge pump circuit and a filter circuit. The charge pump circuit includes a first switch and a second switch. The first switch and the second switch are coupled at a first node and are coupled between a power terminal and a ground terminal. The filter circuit includes a first capacitor, a second capacitor, and a first voltage switching circuit. The first capacitor is coupled between the first node and the ground terminal. The second capacitor is coupled between the first voltage switching circuit and the first node.
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6.发明授权公开(公告)号：US11955979B2
公开(公告)日：2024-04-09
申请号：US17835292
申请日：2022-06-08
申请人： Apple Inc.
发明人： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC分类号： H03L7/0891 , H03C3/0941 , H03L7/091 , H03L7/099 , H03L7/185 , H03L7/1976 , H04L7/033
摘要： An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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公开(公告)号：US11929751B1
公开(公告)日：2024-03-12
申请号：US18148652
申请日：2022-12-30
发明人： Ankit Garg , Abhijit Patki
CPC分类号： H03L7/0807 , H03L7/083 , H03L7/091 , H03L7/10 , H03L7/18
摘要： A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.
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公开(公告)号：US20240022254A1
公开(公告)日：2024-01-18
申请号：US17864593
申请日：2022-07-14
申请人： Intel Corporation
摘要： An apparatus, system, and method for low frequency periodic signaling (LFPS) and/or squelch detection are provided. A circuit can include a threshold generator situated to receive a differential input signal from an initiator device and generate a differential voltage threshold signal based on the differential input signal, an amplifier circuit electrically coupled to the threshold generator situated to amplify the differential voltage threshold signal resulting in an amplified threshold signal, a sampler situated to sample the amplified threshold signal at a first clock rate faster than a clock rate of an LFPS/squelch signaling frequency resulting in digital sample results, and a pattern filter circuit situated to determine if the digital sample results are asserted for each of a specified number of consecutive clock cycles at the first clock rate.
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9.发明公开公开(公告)号：US20240007112A1
公开(公告)日：2024-01-04
申请号：US17895393
申请日：2022-08-25
CPC分类号： H03L7/091 , H03L7/099 , H03L7/0891
摘要： A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.
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公开(公告)号：US20230387920A1
公开(公告)日：2023-11-30
申请号：US17751679
申请日：2022-05-24
发明人： Heng-Chih Lin , Shu-Yu Lin
摘要： A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.
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