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公开(公告)号：US20240283459A1
公开(公告)日：2024-08-22
申请号：US18569459
申请日：2022-06-13
发明人： Carsten WULFF , Tor Øyvind VEDAL , Ola BRUSET , Shankkar BALASUBRAMANIAN , Ruben UNDHEIM , Harald GARVIK
CPC分类号： H03L7/104 , H03L7/093 , H03L7/099 , H03L2207/50
摘要： According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.
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公开(公告)号：US20240275393A1
公开(公告)日：2024-08-15
申请号：US18168544
申请日：2023-02-13
发明人： Jia-Ming HE , Yaw-Guang CHANG , Yu-Han CHEN
CPC分类号： H03L7/0992 , H03L7/101 , H03L7/24
摘要： The invention provides a power system for monitoring a working environment of a monitored circuit and adjusting a working voltage of the monitored circuit includes: a power circuit, a voltage-controlled oscillator and a counter. The power circuit is configured to output the working voltage to the monitored circuit through a power supply path. The voltage-controlled oscillator is disposed in or around the monitored circuit and is electrically connected to the power supply path and a ground path to which the monitored circuit is electrically connected, and is configured to output an oscillation frequency in accordance with a signal variation on the power supply path and the ground path. The counter is electrically connected to the voltage-controlled oscillator and is configured to generate a counting number signal in accordance with the oscillation frequency and a synchronizing signal, thereby adjusting the working voltage outputted to the monitored circuit.
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公开(公告)号：US20240195425A1
公开(公告)日：2024-06-13
申请号：US18582728
申请日：2024-02-21
发明人： Fahim ur RAHMAN , Jinuk SHIN
CPC分类号： H03L7/10 , H03H17/02 , H03L7/0812 , H03L7/093 , H03H2017/0081
摘要： An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.
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公开(公告)号：US20240178846A1
公开(公告)日：2024-05-30
申请号：US18435323
申请日：2024-02-07
发明人： Ankit Garg , Abhijit Patki
CPC分类号： H03L7/0807 , H03L7/083 , H03L7/091 , H03L7/10 , H03L7/18
摘要： A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.
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公开(公告)号：US20240146318A1
公开(公告)日：2024-05-02
申请号：US18544289
申请日：2023-12-18
申请人： Apple Inc.
发明人： Ali Parsa , Ahmed I Hussein
摘要： This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.
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公开(公告)号：US11916559B2
公开(公告)日：2024-02-27
申请号：US18090748
申请日：2022-12-29
发明人： Fahim Ur Rahman , Jinuk Shin
CPC分类号： H03L7/10 , H03H17/02 , H03L7/0812 , H03L7/093 , H03H2017/0081
摘要： A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.
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公开(公告)号：US11831063B2
公开(公告)日：2023-11-28
申请号：US17674572
申请日：2022-02-17
发明人： Yasushi Koyama , Yoshinori Tateishi
IPC分类号： H01Q9/04 , H03B7/08 , H03B7/14 , H01Q9/16 , H01Q21/06 , H03B7/12 , G01R31/311 , H01Q1/38 , G01R31/28 , H03B5/12 , H03L7/099 , H03L7/10 , H03L7/193
CPC分类号： H01Q9/0414 , G01R31/2831 , G01R31/311 , H01Q1/38 , H01Q9/16 , H01Q21/065 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03B7/08 , H03B7/12 , H03B7/146 , H03L7/099 , H03L7/101 , H03L7/103 , H03L7/193 , H03B2200/0084
摘要： An element includes a coupling line in which a first conductor layer, a dielectric layer, and a second conductor layer are stacked in this order, and which is connected to the second conductor layer in order to mutually synchronize a plurality of antennas at a frequency of a terahertz wave; and a bias line connecting a power supply for supplying a bias signal to a semiconductor layer and the second conductor layer. A wiring layer in which the coupling line is formed and a wiring layer in which the bias line is formed are different layers. The bias line is disposed in a layer between the first conductor layer and the second conductor layer.
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公开(公告)号：US11714769B2
公开(公告)日：2023-08-01
申请号：US17724221
申请日：2022-04-19
申请人： Uniquify, Inc.
发明人： Jung Lee , Venkat Iyer , Brett Murdock
IPC分类号： G06F13/362 , G06F13/16 , H03L7/081 , G11C29/02 , H03L7/10 , H03L7/08 , G11C8/18 , H03K5/133 , H03K5/14 , G06F13/42 , H03K5/00
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03L7/08 , H03L7/0812 , H03L7/10 , H03K2005/00019
摘要： A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
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公开(公告)号：USRE49519E1
公开(公告)日：2023-05-02
申请号：US17313352
申请日：2021-05-06
发明人： Rainer Stuhlberger , Lukas Heschl
IPC分类号： H03L7/099 , H03L7/14 , H03G3/30 , H03L7/081 , H03L7/10 , G01S7/35 , G01S13/34 , G01S13/93 , H03C3/09 , H03L7/093 , H03L7/197 , G01S13/931
摘要： A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.
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公开(公告)号：US11632228B2
公开(公告)日：2023-04-18
申请号：US17476782
申请日：2021-09-16
发明人： Jungpil Lim , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
摘要： A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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