公开(公告)号：USRE49519E1

公开(公告)日：2023-05-02

申请号：US17313352

申请日：2021-05-06

申请人： Infineon Technologies AG

发明人： Rainer Stuhlberger ,  Lukas Heschl

IPC分类号： H03L7/099 ,  H03L7/14 ,  H03G3/30 ,  H03L7/081 ,  H03L7/10 ,  G01S7/35 ,  G01S13/34 ,  G01S13/93 ,  H03C3/09 ,  H03L7/093 ,  H03L7/197 ,  G01S13/931

摘要： A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

公开(公告)号：US11606224B2

公开(公告)日：2023-03-14

申请号：US17453054

申请日：2021-11-01

申请人： Robert Bosch GmbH

发明人： Marcel Kneib ,  Oleg Schell

IPC分类号： H04L12/40 ,  H03M1/82 ,  H03L7/14

摘要： A method for checking a message in a communication system, in which multiple users are connected to a communication medium that includes two signal lines and exchange messages via same. A time difference between points in time of reception of a message that is sent on the communication medium is ascertained at two different, predefined positions on the communication medium, and based on a comparison of the time difference to at least one reference time difference, it is determined whether the message originates from a verified user. During the ascertainment of the time difference at the two positions, in each case a difference signal is formed from signals that have resulted on the two signal lines due to the message.

公开(公告)号：US11256287B2

公开(公告)日：2022-02-22

申请号：US16440890

申请日：2019-06-13

申请人： Intel Corporation

发明人： Nathaniel August ,  Muhammed Elgousi ,  Benjamin Gordon ,  Tsai-Yuan Chen

IPC分类号： G06F1/12 ,  H03L7/14 ,  H03B5/32 ,  H03L7/08

摘要： Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.

公开(公告)号：US11177817B2

公开(公告)日：2021-11-16

申请号：US16891405

申请日：2020-06-03

申请人： Electronics and Telecommunications Research Institute

发明人： Seong Mo Park ,  Kyung Hwan Park ,  Tae Wook Kang ,  Byounggun Choi

IPC分类号： H03L7/14 ,  H03L7/089 ,  G06F1/12 ,  G06F7/58 ,  G06F1/08 ,  H03K3/356

摘要： Provided are a random number generating device and a method of operating the same. The random number generating device includes a source detector, a pulse generator, a counter, and a verification circuit. The source detector detects particles emitted from a source to generate a detection signal. The pulse generator generates pulses corresponding to the detected particles, based on the detection signal. The counter measures time intervals among the pulses and generates binary count values respectively corresponding to the time intervals. The verification circuit determines an output of the binary count values, based on the number of 0 values and the number of 1 values included in the binary count values.

公开(公告)号：US11115036B1

公开(公告)日：2021-09-07

申请号：US16991882

申请日：2020-08-12

申请人： QUALCOMM Incorporated

发明人： Shitong Zhao ,  Kevin Jia-Nong Wang ,  Shyam Sivakumar ,  Debesh Bhatta

IPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/24 ,  H03L7/14

摘要： An oscillator including a switched capacitor configured to generate a sawtooth or ramp voltage in response to a switched capacitor drive signal; a low pass filter (LPF) configured to filter the sawtooth or ramp voltage to generate a filtered voltage; a reference voltage generator configured to generate a reference voltage; an integrator configured to integrate a difference between the sawtooth or ramp voltage and the reference voltage to generate a frequency control signal; a voltage controlled oscillator (VCO) configured to generate a first clock based on the frequency control signal; a frequency divider configured to frequency divide the first clock to generate a second clock; and a switched capacitor driver configured to generate the switched capacitor drive signal in response to the second clock. The oscillator may also include a switched capacitor sampler to sample the sawtooth or ramp voltage, wherein the filtered voltage is based on the sampled voltage.

公开(公告)号：US11005481B2

公开(公告)日：2021-05-11

申请号：US16204109

申请日：2018-11-29

申请人： Apple Inc.

发明人： Evgeny Shumaker ,  Gil Horovitz

IPC分类号： H03L7/14 ,  H03L7/087 ,  H03L7/099 ,  H03L7/18 ,  H04L27/00

摘要： A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

公开(公告)号：US10910026B2

公开(公告)日：2021-02-02

申请号：US16834708

申请日：2020-03-30

申请人： Rohm Co., Ltd.

发明人： Takehiro Yoshida ,  Shun Fukushima

IPC分类号： H02M1/00 ,  H02M3/335 ,  G05F1/00 ,  G11C7/22 ,  G11C16/30 ,  G06F1/04 ,  H03L7/081 ,  H03L7/14 ,  G11C16/12

摘要： A clock generation circuit, which generates an output clock using an external clock as a target clock, includes a circuit arranged to change the output clock to high level in synchronization with an up edge of the target clock, circuits arranged to generate first and second ramp voltages with a period of interval between neighboring up edges of the target clock, and a circuit arranged to hold a comparison voltage corresponding to a second ramp voltage when an up edge of the target clock occurs. The level of the output clock is changed from high level to low level based on a comparison result between the first ramp voltage and the comparison voltage.

公开(公告)号：US10897225B1

公开(公告)日：2021-01-19

申请号：US16583898

申请日：2019-09-26

申请人： International Business Machines Corporation

发明人： James Strom ,  Matthew James Paschal ,  Bruce George Rudolph ,  Daniel M. Dreps

IPC分类号： H03B5/06 ,  H03L7/14 ,  G01R31/28 ,  G06F1/04 ,  H03K23/58 ,  H03K5/19

摘要： A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

公开(公告)号：US20200321969A1

公开(公告)日：2020-10-08

申请号：US16908786

申请日：2020-06-23

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Jayawardan JANARDHANAN ,  Christopher Andrew SCHELL ,  Arvind SRIDHAR ,  Sinjeet Dhanvantray PAREKH

IPC分类号： H03L7/093 ,  H03L7/14 ,  H03L7/087 ,  H03L7/083

摘要： A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

公开(公告)号：US10771012B2

公开(公告)日：2020-09-08

申请号：US16587509

申请日：2019-09-30

申请人： Microchip Technology Incorporated

发明人： Jason Sachs

IPC分类号： H03B5/32 ,  H03L7/14 ,  H03B5/20

摘要： An oscillator includes a tunable oscillator, a phase detector circuit communicatively coupled with an output of the tunable oscillator and an input to the oscillator, and an oscillator controller circuit configured to adjust frequency of the tunable oscillator based upon phase detection between output of the tunable oscillator and output of an external resonant element received at the input to the oscillator.