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公开(公告)号：US20240305309A1
公开(公告)日：2024-09-12
申请号：US18180933
申请日：2023-03-09
申请人： Dell Products L.P.
CPC分类号： H03M1/1285 , H03M1/145 , H03M1/361
摘要： A timing signal diagnostic system includes a chassis housing an input system that receives a timing signal, a timing system that receives the timing signal from the input system, an analog-to-digital converter system that receives the timing signal from the input system, and a processing system that is coupled to the timing system and the analog-to-digital converter system. The processing system uses the timing system to output reference time signals to the analog-to-digital converter system that are based on the timing signal, and uses the analog-to-digital converter system to sample the timing signal based on the reference time signals over a plurality of different timing signal cycles. Based on the sampling of the timing signal, the processing system generates a waveform for the timing signal, and provides a timing signal diagnostic result based on the waveform for the timing signal.
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公开(公告)号：US20240283460A1
公开(公告)日：2024-08-22
申请号：US18171211
申请日：2023-02-17
发明人： Rui Wang , Hiroaki Ebihara
摘要： A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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公开(公告)号：US12052028B2
公开(公告)日：2024-07-30
申请号：US17844413
申请日：2022-06-20
申请人： SILEAD Inc.
发明人： Jinling Zhou
CPC分类号： H03M1/462 , H03K19/1774 , H03K19/20 , H03M1/206 , H03M1/361
摘要： A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.
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公开(公告)号：US11742872B2
公开(公告)日：2023-08-29
申请号：US17728985
申请日：2022-04-26
发明人： Eizo Ichihara , Shintaro Kawazoe
CPC分类号： H03M1/1245 , H03M1/0854 , H03M1/361 , H03M1/50 , H03M3/39
摘要： Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.
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公开(公告)号：US11705919B2
公开(公告)日：2023-07-18
申请号：US17439516
申请日：2020-03-02
摘要： An analog-to-digital circuit that digitizes an analog voltage. The analog-to-digital circuit includes plural comparators functionally connected to form a tree that has levels i, and each level i has branches j, and an encoder connected to the plural comparators and configured to generate a digitized value of an input analog voltage. Each comparator from a level i has first and second outputs, and each of the first and second outputs is electrically connected to an input of different comparators from a next level i+1 of the tree.
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6.发明公开公开(公告)号：US20230188150A1
公开(公告)日：2023-06-15
申请号：US17972669
申请日：2022-10-25
发明人： SHIH-HSIUNG HUANG
IPC分类号： H03M1/12 , H03M1/36 , H03K19/17736
CPC分类号： H03M1/1245 , H03M1/368 , H03K19/1774
摘要： The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.
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公开(公告)号：US11664814B2
公开(公告)日：2023-05-30
申请号：US17461400
申请日：2021-08-30
CPC分类号： H03M1/203 , G06G7/30 , H03F3/45183 , H03M1/365
摘要： Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.
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公开(公告)号：US20230087101A1
公开(公告)日：2023-03-23
申请号：US17886033
申请日：2022-08-11
发明人： Yoichi IIZUKA , Fukashi MORISHITA
摘要： An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.
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公开(公告)号：US11581895B2
公开(公告)日：2023-02-14
申请号：US17431888
申请日：2019-02-27
发明人： Henrik Fredriksson , Henrik Sjöland
摘要： An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).
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公开(公告)号：US11575386B2
公开(公告)日：2023-02-07
申请号：US17315699
申请日：2021-05-10
申请人： Rambus Inc.
发明人： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
摘要： A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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