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公开(公告)号：US12184302B2
公开(公告)日：2024-12-31
申请号：US17994803
申请日：2022-11-28
Applicant: SILEAD Inc.
Inventor： Jinling Zhou
Abstract: A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a first logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.
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公开(公告)号：US20240421827A1
公开(公告)日：2024-12-19
申请号：US18336526
申请日：2023-06-16
Applicant: Renesas Design Technology Inc.
Inventor： Vladyslav KOZLOV , Dmytro MYMRIKOV
Abstract: An analog to digital converter for converting an analog signal to a digital signal by sampling the analog signal to generate the digital signal, the analog to digital converter being configured to acquire a first sample comprising a first plurality of bits that is representative of the digital signal, determine one or more bit positions within the first plurality of bits that are variable, determine one or more bit positions within the first plurality of bits that are static, and acquire a second sample after having acquired the first sample, the second sample comprising a second plurality of bits that is representative of the digital signal, wherein for the acquisition of the second sample at least a portion of the one or more bit positions that are variable have their bit values generated by sampling of the analog signal, and each of the one or more bit positions that are static have their bit values set to the same bit value as the bit value of the corresponding bit position in the first sample.
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公开(公告)号：US12166459B2
公开(公告)日：2024-12-10
申请号：US18232526
申请日：2023-08-10
Inventor： Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
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公开(公告)号：US12143117B2
公开(公告)日：2024-11-12
申请号：US17870983
申请日：2022-07-22
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Shih-Hsiung Huang
Abstract: A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion. The encoder circuit generates a digital output according to a corresponding coarse digital code and the fine digital code.
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公开(公告)号：US20240340019A1
公开(公告)日：2024-10-10
申请号：US18745800
申请日：2024-06-17
Applicant: AyDeeKay LLC dba Indie Semiconductor
Inventor： Christopher A. Menkus , Robert W. Kim
Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
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Patent Agency Ranking
公开(公告)号：US12113544B2
公开(公告)日：2024-10-08
申请号：US17864464
申请日：2022-07-14
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Sheng-Yen Shih , Shih-Hsiung Huang , Wei-Cian Hong
CPC classification number: H03M1/38 , H03M1/1245 , H03M3/04
Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.
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公开(公告)号：US20240333297A1
公开(公告)日：2024-10-03
申请号：US18612301
申请日：2024-03-21
Applicant: ROHM CO., LTD.
Inventor： Naohiro NOMURA
IPC: H03M1/38
CPC classification number: H03M1/38
Abstract: A successive approximation type A/D converter includes: a capacitive D/A converter, and a buffer circuit configured to supply a reference voltage to the capacitive D/A converter, wherein the buffer circuit includes: a reference voltage source configured to generate a constant voltage, a first stage amplifier configured to amplify the constant voltage, an output buffer with a gain of 1 configured to receive a voltage according to an output voltage of the first stage amplifier, and a filter that is interposed between the first stage amplifier and the output buffer and acts on a signal directed from the output buffer to the first stage amplifier, and wherein a tail current of a differential amplifier of the output buffer is larger than a tail current of a differential amplifier of the first stage amplifier.
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公开(公告)号：US12047087B2
公开(公告)日：2024-07-23
申请号：US17771268
申请日：2019-10-31
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Tadashi Minotani , Kenichi Matsunaga
Abstract: An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
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公开(公告)号：US20240192575A1
公开(公告)日：2024-06-13
申请号：US18532400
申请日：2023-12-07
Applicant: LX SEMICON CO., LTD.
Inventor： Hyung Seup KIM , Kyu Ho KIM , Dong Hwan YOON , Jin Kook YUN , Dong Gil JEONG
CPC classification number: G03B5/00 , H03K5/003 , H03M1/38 , G03B2205/0007
Abstract: An analog front-end circuit includes a hall bias correction loop circuit configured to correct a sensing voltage of a hall sensor by adjusting a hall bias current flowing in the hall sensor while tracking a change in the sensing voltage of the hall sensor based on a temperature change, an offset correction loop circuit configured to correct an offset correction voltage while tracking an offset change of the hall sensor and an offset change of an amplifier circuit based on the temperature change, the amplifier circuit configured to amplify and output the sensing voltage of the hall sensor, corrected through at least one of the hall bias correction loop circuit and the offset correction loop circuit, and an analog-digital converter configured to convert an output voltage of the amplifier circuit into sensing data and output the sensing data.
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公开(公告)号：US20240187014A1
公开(公告)日：2024-06-06
申请号：US18285217
申请日：2022-03-31
Applicant: Nordic Semiconductor ASA
Inventor： Henrik FON
Abstract: A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.
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