SAMPLE AND HOLD READOUT SYSTEM AND METHOD FOR RAMP ANALOG TO DIGITAL CONVERSION

    公开(公告)号:US20250056139A1

    公开(公告)日:2025-02-13

    申请号:US18925810

    申请日:2024-10-24

    Abstract: A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.

    SINGLE SLOPE ANALOGUE-DIGITAL CONVERTER AND METHOD PERFORMING THEREOF

    公开(公告)号:US20240259032A1

    公开(公告)日:2024-08-01

    申请号:US18161276

    申请日:2023-01-30

    Inventor: Hyeon Joon Kim

    CPC classification number: H03M1/56 H03M1/125

    Abstract: Disclosed herein is a method of operating a single slope analog-to-digital converter (ADC), which includes receiving an input signal from a sensor or a ramp signal from a ramp generator according to a state of a switch and sampling the received input or ramp signal, comparing, by a comparator, whether the sampled ramp signal is present in a predetermined input range in a state in which the ramp generator maintains an off state and outputting the comparison result, generating, by a logic part, a flag signal indicating a high or low according to the comparison result by the comparator and providing the flag signal to the ramp generator, and sampling, by the ramp generator, a reference voltage of the comparator according to the flag signal based on an off or on state.

    IMAGING DEVICE AND ANALOG-TO-DIGITAL CONVERSION CIRCUIT

    公开(公告)号:US20240236526A9

    公开(公告)日:2024-07-11

    申请号:US18548278

    申请日:2022-02-01

    Inventor: Yusuke Togasaki

    CPC classification number: H04N25/772 H03M1/56 H04N25/7795

    Abstract: An imaging device of the present disclosure includes a first pixel circuit and a generation circuit. The first pixel circuit includes a first light-receiving circuit, a first comparator, a first control circuit, and a first latch circuit. The first light-receiving circuit is configured to generate a first pixel signal corresponding to the amount of received light. The first comparator is configured to generate a first comparison signal by comparing the first pixel signal with a first reference signal having a ramp waveform. The first control circuit is configured to generate a first comparison output signal by turning on and off an output of the first comparison signal on the basis of a first control signal. The first latch circuit is configured to latch a time code on the basis of transition of the first comparison output signal. The generation circuit is configured to generate the first control signal.

    Gas concentration detection device

    公开(公告)号:US11953467B2

    公开(公告)日:2024-04-09

    申请号:US17403601

    申请日:2021-08-16

    Inventor: Mitsuru Aoki

    CPC classification number: G01N27/626 G01N33/0027 H03M1/56

    Abstract: A gas concentration detection device includes: a gas concentration sensor having a gas sensor element that outputs an electric signal according to a gas concentration and a heater that heats the gas sensor element; a heater controller controlling energization and de-energization of the heater; a sensor controller having an ADC AD-converting the electric signal from an analog signal to a digital signal in synchronization with a sampling clock (fs) and detecting the gas concentration based on an output signal of the AD converter; and a timing adjuster shifting a switching timing of energization control from a conversion timing at which the AD converter performs the AD conversion.

    SYSTEM AND METHODS FOR RAMP CONTROL
    8.
    发明公开

    公开(公告)号:US20240022257A1

    公开(公告)日:2024-01-18

    申请号:US18095933

    申请日:2023-01-11

    CPC classification number: H03M1/56

    Abstract: A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.

    IMAGING DEVICE AND ELECTRONIC APPARATUS
    9.
    发明公开

    公开(公告)号:US20230336894A1

    公开(公告)日:2023-10-19

    申请号:US18042240

    申请日:2021-08-11

    Inventor: SACHIO AKEBONO

    Abstract: An imaging device according to the present disclosure includes a light-receiving pixel; a reference signal generator; a first amplification section; a second amplification section; a third amplification section; and a counter. The first amplification section is coupled to a first power supply node and a second power supply node. The first amplification section performs a comparison operation on the basis of a pixel signal and a reference signal. The first amplification section outputs a signal corresponding to a result of the comparison to a first node. The second amplification section includes a first transistor and a first load circuit. The first transistor includes a gate coupled to the first node, a drain coupled to a second node, and a source coupled to the second power supply node. The third amplification section includes a second transistor and a first switch. The second transistor includes a gate coupled to the second node, a source coupled to the first power supply node, and a drain coupled to a third node. The first switch applies a predetermined voltage to the third node by being turned on. The counter is coupled to a third power supply node and a fourth power supply node. The counter stops a count operation on the basis of a voltage of the third node.

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