公开(公告)号：US20240356565A1

公开(公告)日：2024-10-24

申请号：US18643302

申请日：2024-04-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kangseok Lee ,  Bohwan Jun ,  Youngjun Hwang ,  Dongmin Shin

IPC分类号： H03M13/11 ,  H03M13/15 ,  H03M13/37

CPC分类号： H03M13/1174 ,  H03M13/1575 ,  H03M13/3746

摘要： An example operating method of an error correction code (ECC) circuit includes receiving a codeword from a memory device, calculating a syndrome vector based on the codeword and a parity-check matrix indicating whether messages are exchanged between check nodes and variable nodes, performing, when the syndrome vector is not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by decoding a first column in a first operation mode, the first column having a first variable node degree, decoding a second column in a second operation mode, the second column having a second variable node degree, and decoding a third column in a third operation mode, the third column having a third variable node degree, and calculating the syndrome vector whenever the sequential decoding of the plurality of columns is completed and iteratively performing the sequential decoding until the syndrome vector is the zero vector.

公开(公告)号：US20240354026A1

公开(公告)日：2024-10-24

申请号：US18758295

申请日：2024-06-28

申请人： NantCell, Inc.

发明人： Aaron Randolph BASSETT

IPC分类号： G06F3/06 ,  G06F21/62 ,  H03M13/15

CPC分类号： G06F3/0652 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/064 ,  G06F3/067 ,  G06F3/0683 ,  G06F21/6254 ,  H03M13/1515

摘要： A geographically distributed erasure coding system includes multiple computer readable, non-transitory storage memories capable of storing a digital dataset including multiple object blocks, where each storage memory is configured to store one or more of the object blocks of the dataset according to an erasure coding policy. The system includes one or more processors configured to implement the erasure coding policy by distributing the multiple object blocks of the dataset to the multiple storage memories according to distribution criteria of the erasure coding policy, and the distribution criteria include at least one status parameter associated with each storage memory. The multiple storage memories are geographically distributed at different locations from one another.

公开(公告)号：US12126358B2

公开(公告)日：2024-10-22

申请号：US17815624

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Lien Linus Lu

IPC分类号： H03M13/11 ,  G11C29/42 ,  G11C29/44 ,  H03M13/15 ,  H03M13/29

CPC分类号： H03M13/1148 ,  G11C29/42 ,  G11C29/44 ,  H03M13/1174 ,  H03M13/1575 ,  H03M13/29

摘要： A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.

公开(公告)号：US20240348267A1

公开(公告)日：2024-10-17

申请号：US18134690

申请日：2023-04-14

申请人： Microsoft Technology Licensing, LLC

发明人： Brett K. DODDS ,  Terry M. GRUNZKE

IPC分类号： H03M13/15 ,  H03M13/00

CPC分类号： H03M13/35 ,  H03M13/353 ,  H03M13/356 ,  H03M13/151 ,  H03M13/611

摘要： A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.

公开(公告)号：US12119075B2

公开(公告)日：2024-10-15

申请号：US18185198

申请日：2023-03-16

申请人： Kioxia Corporation

发明人： Avi Steiner ,  Ofir Kanter ,  Yasuhiko Kurosawa

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C29/02 ,  G11C29/52 ,  H03M13/11 ,  H03M13/15

CPC分类号： G11C29/52 ,  G11C29/022 ,  G11C29/024

摘要： Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

公开(公告)号：US12111723B2

公开(公告)日：2024-10-08

申请号：US18233250

申请日：2023-08-11

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely Tsern

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C7/10 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  H03M13/15 ,  G06F11/20

CPC分类号： G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  H03M13/1575 ,  G06F11/20 ,  G11C2029/4402 ,  G11C29/765

摘要： A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US12105588B2

公开(公告)日：2024-10-01

申请号：US17804483

申请日：2022-05-27

申请人： Pure Storage, Inc.

发明人： Yogesh R. Vedpathak ,  Ramin Rouzbeh ,  Jason K. Resch

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F21/10 ,  G06F21/44 ,  G06F21/60 ,  G06F21/62 ,  G06F21/64 ,  G06F21/80 ,  H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H04L9/00 ,  H04L9/08 ,  H04L9/32 ,  H04L67/10 ,  H04L67/1097 ,  H04L67/306 ,  H04L67/50 ,  H04L67/52 ,  H04L67/60 ,  G06F11/07 ,  H03M13/15

CPC分类号： G06F11/1076 ,  G06F11/1044 ,  G06F11/1092 ,  G06F11/142 ,  G06F11/2094 ,  G06F21/10 ,  G06F21/44 ,  G06F21/60 ,  G06F21/602 ,  G06F21/6218 ,  G06F21/6272 ,  G06F21/645 ,  G06F21/805 ,  H03M13/2909 ,  H03M13/3761 ,  H03M13/611 ,  H04L9/006 ,  H04L9/0841 ,  H04L9/085 ,  H04L9/0861 ,  H04L9/0894 ,  H04L9/3271 ,  H04L67/10 ,  H04L67/1097 ,  H04L67/306 ,  H04L67/52 ,  H04L67/535 ,  H04L67/60 ,  G06F11/0712 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/1004 ,  H03M13/1515 ,  H03M13/616 ,  H04L2209/34

摘要： A method includes writing sets of encoded data slices to storage units of a storage network in accordance with error encoding parameters, where for a set of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number, the error coding number indicates a number of encoded data slices that results when a data segment is encoded using an error encoding function and the decode threshold number indicates a minimum number needed to recover the data segment. The method further includes monitoring processing of the writing the sets of encoded data slices to produce write processing performance information. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent encoded data slices.

公开(公告)号：US20240322843A1

公开(公告)日：2024-09-26

申请号：US18611441

申请日：2024-03-20

申请人： Microchip Technology Incorporated

发明人： Diego Felipe Gomes Coelho ,  Peter Graumann

IPC分类号： H03M13/15 ,  G06F17/16

CPC分类号： H03M13/153 ,  G06F17/16 ,  H03M13/1515

摘要： A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.

公开(公告)号：US20240322842A1

公开(公告)日：2024-09-26

申请号：US18735554

申请日：2024-06-06

申请人： Electronics and Telecommunications Research Institute

发明人： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM

IPC分类号： H03M13/15 ,  H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29

CPC分类号： H03M13/152 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1165 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/6393 ,  H03M13/6552

摘要： A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

公开(公告)号：US12095480B1

公开(公告)日：2024-09-17

申请号：US18210458

申请日：2023-06-15

申请人： Astera Labs, Inc.

发明人： Enrique Musoll ,  Anh T. Tran ,  Subbarao Arumilli ,  Chi Feng

IPC分类号： H03M13/15 ,  G11C29/36 ,  G11C29/42 ,  H03M13/09

CPC分类号： H03M13/1575 ,  G11C29/36 ,  G11C29/42 ,  H03M13/095 ,  H03M13/1515 ,  G11C2029/3602

摘要： A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.