公开(公告)号：US12225309B2

公开(公告)日：2025-02-11

申请号：US18297721

申请日：2023-04-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Tetsuya Itano ,  Kohichi Nakamura ,  Daisuke Kobayashi

IPC: H04N25/75 ,  H03M3/00 ,  H04N25/42

Abstract: A photoelectric conversion apparatus includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ΔΣ A/D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change a gain of the photoelectric conversion apparatus in accordance with a change of a driving mode of the photoelectric conversion apparatus. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ΔΣ A/D converter. The control circuit changes the gain of the photoelectric conversion apparatus by changing a resistance value of the variable resistor.

公开(公告)号：US20250030436A1

公开(公告)日：2025-01-23

申请号：US18399223

申请日：2023-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand SUBRAMANIAN ,  Tanmay HALDER ,  Deepa NAIR J S ,  Sreeja CHAKINGAL

IPC: H03M3/00

Abstract: In a described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third DAC outputs. Synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. Selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.

公开(公告)号：US12206437B2

公开(公告)日：2025-01-21

申请号：US17988696

申请日：2022-11-16

Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Jae Yoon Sim ,  Kyu Jin Choi

IPC: H03M3/00 ,  H03M1/80

Abstract: The present disclosure relates to a time-division multiplexing (TDM)-based multi-channel electrocardiogram measurement apparatus and method, which remove the influence of power line interference in a way to implement multiple channels by using a TDM method, remove an electrode DC offset (EDO) through a pre-charged capacitor, and periodically take a current out or supply a current. The TDM-based multi-channel electrocardiogram measurement apparatus and method robust against power line interference according to the present disclosure have advantages in that it can measure electrocardiogram by using multiple channels with low power and high integration based on TDM, can perform contactless measurement because an EDO is efficiently eliminated and high impedance is satisfied, and has a characteristic robust against power line interference.

公开(公告)号：US20250015814A1

公开(公告)日：2025-01-09

申请号：US18218366

申请日：2023-07-05

Applicant: NXP B.V.

Inventor： Maarten Jelmar MOLENDIJK ,  Robert van VELDHOVEN

IPC: H03M3/00

Abstract: A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

公开(公告)号：US20240429881A1

公开(公告)日：2024-12-26

申请号：US18739569

申请日：2024-06-11

Applicant: STMicroelectronics International N.V.

Inventor： Edoardo BOTTI ,  Francesco STILGENBAUER ,  Matteo DE FERRARI ,  Edoardo BONIZZONI ,  Piero MALCOVATI

IPC: H03F3/217 ,  H03F3/183 ,  H03M3/00

Abstract: Signal processing is applied to a digital input audio signal. An analog audio output signal is provided based on the digital input audio signal via a switching converter circuit driven by a PWM signal. The analog audio output signal is sensed to generate an analog feedback signal. The applied signal processing includes: producing a digital error signal indicative of a difference between the digital input audio signal and a digital word signal; applying digital-to-analog conversion to the digital error signal to produce an analog replica of the digital error signal; producing an analog difference signal indicative of a difference between the analog replica of the digital error signal and the analog feedback signal; applying analog-to-digital conversion to the analog difference signal to produce the digital word signal; applying digital filtering to the digital word signal to produce a filtered digital word signal that generates the PWM signal.

公开(公告)号：US12177604B2

公开(公告)日：2024-12-24

申请号：US18093802

申请日：2023-01-05

Applicant: Maxim Integrated Products, Inc.

Inventor： Yalcin Balcioglu

IPC: H04N7/12 ,  G06F1/04 ,  H03M3/00 ,  H04L7/033 ,  H04N7/10 ,  H04N21/234 ,  H04N21/2365 ,  H04N21/414 ,  H03L7/193 ,  H03L7/197

Abstract: Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

公开(公告)号：US12170523B2

公开(公告)日：2024-12-17

申请号：US17997967

申请日：2021-04-27

Applicant: Agency for Science, Technology and Research

Inventor： Tantan Zhang ,  Yuan Gao

IPC: H03M1/46 ,  H03M3/00 ,  H03M1/66

Abstract: This disclosure relates to a current-to-digital converter suitable for wide-ranging current sensing applications. In particular, the current-to-digital converter comprises a delta-sigma analogue-to-digital converter which utilizes a successive-approximation-register to control a modulation of the sensed current so that the digital conversion of the modulated sensed current by the delta-sigma analogue-to-digital converter may be done with high precision.

公开(公告)号：US20240403495A1

公开(公告)日：2024-12-05

申请号：US18517348

申请日：2023-11-22

Applicant: Microsemi SoC Corp.

Inventor： Gerald Richard Newell

IPC: G06F21/75 ,  G06F17/14 ,  H03M3/00

Abstract: Methods and systems for tamper detection based on power network electrical characteristic by storing a reference electrical signature of a power distribution network comprising the integrated circuit, generating in the integrated circuit a current stimulus waveform by sigma-delta based noise shaping, and providing the waveform to the power distribution network comprising the integrated circuit, sampling the power distribution network with a voltage-to-digital converter in the integrated circuit and estimating based at least partially on the sampled power distribution network a response electrical signature of the power distribution network responsive to the stimulus waveform, comparing on the integrated circuit the estimated response electrical signature and the reference electrical signature, and triggering by the integrated circuit a penalty based on a comparison of the response electrical signature and the reference electrical signature.

公开(公告)号：US20240388308A1

公开(公告)日：2024-11-21

申请号：US18786120

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Martin Kinyua ,  Eric Soenen

IPC: H03M3/00 ,  H03K3/03

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

公开(公告)号：US20240388307A1

公开(公告)日：2024-11-21

申请号：US18658328

申请日：2024-05-08

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Masaaki Tanio

IPC: H03M3/00

Abstract: A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.