公开(公告)号：US06348882B1

公开(公告)日：2002-02-19

申请号：US09625084

申请日：2000-07-25

申请人： John Charles Ciccone ,  D.C. Sessions ,  Carl Liepold

发明人： John Charles Ciccone ,  D.C. Sessions ,  Carl Liepold

IPC分类号： H03M520

CPC分类号： H04L25/0292 ,  H03M7/00 ,  H03M7/06 ,  H04L25/0274

摘要： A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.

摘要翻译： 提供信号转换器，用于将多电平编码的数字信号转换为二进制等效信号。 信号转换器包括参考电压发生器，多个四输入差分比较器，定时恢复电路和信号转换电路。 参考电压发生器用于产生多个逐渐变大的差分参考电压。 多个差分比较器各自用于将差分输入电压的幅度与逐渐变大的差分参考电压中的专用差分输入电压的幅度进行比较，并且如果差分输入电压的幅度更大则产生具有第一逻辑检测的差分输出电压 如果差分输入电压的幅度小于差分参考电压的幅度，则具有第二逻辑检测​​。 每个比较器具有偏移输入电压。 定时恢复电路被配置为从每个差分比较器接收差分输出电压，并且可操作以经由边沿检测导出时钟并产生恢复的时钟信号。 信号转换电路与定时恢复电路和差分比较器耦合，并且可操作地将差分输出电压转换为二进制等效。 还提供了一种方法。

公开(公告)号：US06604219B1

公开(公告)日：2003-08-05

申请号：US09496897

申请日：2000-02-02

申请人： David C. Lee ,  John L. Fan ,  Yung-Cheng Lo

发明人： David C. Lee ,  John L. Fan ,  Yung-Cheng Lo

IPC分类号： H03M520

CPC分类号： H04L25/4919 ,  G11B7/0045 ,  G11B7/013 ,  G11B20/10 ,  G11B20/1496 ,  G11B20/18 ,  G11B2020/1457 ,  H03M13/09

摘要： A system and method are disclosed for writing a multilevel data sequence to a storage medium so that a read signal generated by reading the multilevel data sequence from the storage medium will have reduced low frequency content is described. The method includes evaluating the effect of a plurality of candidate merge symbols on an RDS of the read signal. A preferred merge symbol is selected from among the plurality of candidate merge symbols based on the effect of the preferred merge symbol on an RDS of the read signal. The preferred merge symbol is added to the multilevel data sequence so that the RDS of the read signal is controlled.

摘要翻译： 公开了一种用于将多级数据序列写入存储介质的系统和方法，以便通过从存储介质读取多级数据序列而产生的读取信号将具有降低的低频内容。 该方法包括评估多个候选合并符号对读取信号的RDS的影响。 基于优选合并符号对读取信号的RDS的影响，从多个候选合并符号中选择优选合并符号。 优选的合并符号被添加到多级数据序列，使得读取信号的RDS被控制。

公开(公告)号：US06522269B2

公开(公告)日：2003-02-18

申请号：US09938082

申请日：2001-08-23

申请人： Jean-Claude Abbiate ,  Alain Blanc ,  Francois Le Maut

发明人： Jean-Claude Abbiate ,  Alain Blanc ,  Francois Le Maut

IPC分类号： H03M520

CPC分类号： H03M5/16

摘要： The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.