公开(公告)号：US06437715B1

公开(公告)日：2002-08-20

申请号：US09932352

申请日：2001-08-17

申请人： Michael Frederic Cowlishaw

发明人： Michael Frederic Cowlishaw

IPC分类号： H03M704

CPC分类号： H03M7/12

摘要： A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

摘要翻译： 提供了一种用于从十进制到二进制进行编码的系统和方法。 编码是以10位二进制位数表示3位十进制数，是Chen-Ho算法的开发。 这提供了> 99％的存储效率，但仍允许十进制算术容易地执行。 十进制输入通常首先转换为二进制编码十进制（每十进制数4位），然后再压缩为10位。 采用本发明的编码方式，如果前导（最高有效）十位数为零，则二进制输出的前三位为零; 如果前两位十进制数为零，则二进制输出的前六位为零。 因此，相同的编码可以灵活地用于将2个十进制数字编码为7个二进制位，以及1个十进制数到4个二进制位。 这使得它特别适用于基于两个（16位，32位，64位等）功率的标准计算机体系结构，因此不能被7或10直接整除。

公开(公告)号：US06369725B1

公开(公告)日：2002-04-09

申请号：US09669226

申请日：2000-09-26

申请人： Fadi Y. Busaba

发明人： Fadi Y. Busaba

IPC分类号： H03M704

CPC分类号： A61M15/0086 ,  A61M11/06 ,  A61M15/0015 ,  A61M15/0018 ,  A61M16/06 ,  A61M16/08 ,  A61M16/208 ,  H03M7/04

摘要： An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number of multiplications necessary to complete the conversion process by first determining the number of leading zeroes. The method then divides the N-bit number into 12-bit segments where each segment is represented as a binary coded decimal number. The method then multiplies at least one binary coded decimal number by a variable in response to the number of multiplications to determine the resulting decimal value.

摘要翻译： 本发明的示例性实施例是用于将数字从二进制转换为十进制的方法和系统。 该方法包括获得N位二进制数，然后通过首先确定前导零的数目来确定完成转换处理所需的乘法数。 该方法然后将N位数分为12位段，其中每个段被表示为二进制编码的十进制数。 然后，该方法响应于乘法数乘以至少一个二进制编码的十进制数乘以变量以确定所得的十进制值。

公开(公告)号：US06809666B1

公开(公告)日：2004-10-26

申请号：US09639520

申请日：2000-08-15

申请人： Odutola Oluseye Ewedemi ,  David Xiao Dong Yang ,  Xi Peng

发明人： Odutola Oluseye Ewedemi ,  David Xiao Dong Yang ,  Xi Peng

IPC分类号： H03M704

CPC分类号： H04N1/00307 ,  H04N5/232 ,  H04N5/235 ,  H04N7/142 ,  H04N2201/0068

摘要： An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

摘要翻译： 图像传感器包括传感器阵列，用于存储像素数据的数据存储器和像素归一化电路。 传感器阵列具有像素元件的二维阵列，并输出数字信号作为表示场景图像的像素数据。 由传感器阵列输出的像素数据以传感器位排列方式排列，并且像素归一化电路将像素数据重排为像素位顺序。 在另一个实施例中，图像传感器包括传感器阵列，数据存储器和像素归一化电路，全部制造在单个集成电路上。 像素归一化电路包括像素重排电路，格雷码二进制转换电路，复位减法电路和多采样归一化电路中的一个或多个。 最后，提供了一个格雷码到二进制转换电路，用于高速转换。

公开(公告)号：US06617986B2

公开(公告)日：2003-09-09

申请号：US09682449

申请日：2001-09-04

申请人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

发明人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

IPC分类号： H03M704

CPC分类号： H03M7/16 ,  H03M7/165

摘要： A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

公开(公告)号：US06489901B1

公开(公告)日：2002-12-03

申请号：US09944738

申请日：2001-08-31

申请人： Anand Venkitachalam ,  Dylan Hester ,  Joe Welser ,  Rajendra Datar ,  Krishnan Subramoniam

发明人： Anand Venkitachalam ,  Dylan Hester ,  Joe Welser ,  Rajendra Datar ,  Krishnan Subramoniam

IPC分类号： H03M704

CPC分类号： H03H17/0294

摘要： A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

摘要翻译： 采样率转换器210,209包括用于响应于由时钟使​​能信号控制的时钟来处理数字数据的滤波器210，滤波器210以第一采样率接收数字数据并以第二采样率输出数字数据。 重采样器电路209产​​生具有接近第一采样率和第二采样率之间的比率的第一占空比的时钟使能信号的第一选定周期。 选择性地，生成具有第二占空比的选择的时钟使能信号的周期，以最小化在时钟使能信号的第一选定周期上累积的误差。

公开(公告)号：US06801143B2

公开(公告)日：2004-10-05

申请号：US10186564

申请日：2002-06-28

申请人： Ashwani Oberai ,  Kavitha A. Prasad ,  Sreenath Kurupati

发明人： Ashwani Oberai ,  Kavitha A. Prasad ,  Sreenath Kurupati

IPC分类号： H03M704

CPC分类号： H03M7/16 ,  G06F5/10 ,  G06F2205/102

摘要： A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

公开(公告)号：US06525679B1

公开(公告)日：2003-02-25

申请号：US10152282

申请日：2002-05-20

申请人： Michael Frederic Cowlishaw

发明人： Michael Frederic Cowlishaw

IPC分类号： H03M704

CPC分类号： H03M7/12

摘要： A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code a decimal digit is binary bits and 1 decimal digit is 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

摘要翻译： 提供了一种用于从十进制到二进制进行编码的系统和方法。 编码是以10位二进制位数表示3位十进制数，是Chen-Ho算法的开发。 这提供了> 99％的存储效率，但仍允许十进制算术容易地执行。 十进制输入通常首先转换为二进制编码十进制（每十进制数4位），然后再压缩为10位。 采用本发明的编码方式，如果前导（最高有效）十位数为零，则二进制输出的前三位为零; 如果前两位十进制数为零，则二进制输出的前六位为零。 因此，相同的编码可以灵活地用于编码十进制数字，是二进制位，1位十进制数是4位二进制位。 这使得它特别适用于基于两个（16位，32位，64位等）功率的标准计算机体系结构，因此不能被7或10直接整除。

公开(公告)号：US06473008B2

公开(公告)日：2002-10-29

申请号：US09777345

申请日：2001-02-06

申请人： Clifford Mark Kelly ,  Marc Auerbach ,  Jonathan Fitch

发明人： Clifford Mark Kelly ,  Marc Auerbach ,  Jonathan Fitch

IPC分类号： H03M704

CPC分类号： G11C27/02 ,  A61B5/0002 ,  A61B5/0428 ,  A61B5/7257 ,  A61B2560/0209

摘要： A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

摘要翻译： 采样系统包括用于接收具有信号分量和可能的噪声分量的数据信号的输入端。 采样器以响应于控制信号设置的采样率采样数据信号。 噪声检测器检测噪声分量的存在，并且如果检测到噪声分量，则产生调节采样器的控制信号，以对于包括噪声分量的数据信号满足奈奎斯特准则的第一采样率采样数据信号，以及 否则产生调节采样器的控制信号，以对于仅包括信号分量的数据信号以满足奈奎斯特准则的第二数据速率采样数据信号。

公开(公告)号：US06191711B1

公开(公告)日：2001-02-20

申请号：US09258027

申请日：1999-02-25

申请人： Kent W. Smith

发明人： Kent W. Smith

IPC分类号： H03M704

CPC分类号： H03M7/3088 ,  H03M7/30

摘要： A system includes an input, a character set mapping function and a character set compression function. The input receives binary data that includes a plurality of binary data bits that may be organized into a plurality of binary data bytes. The character set mapping function maps the binary data bits into a predetermined character set to produce a plurality of characters. The character set compression function compresses the plurality of characters using a character set compression algorithm to produce a plurality of compressed characters. After compression of the character set data, the plurality of compressed characters may be modulated via a modem and transmitted across a data link to a receiving location. At the receiving location, a demodulator receives the modulated data and demodulates the modulated data to produce the plurality of compressed characters. Then, a character set decompression function decompresses the plurality of compressed characters to produce a plurality of characters. A binary data extraction function then extracts the binary data from the plurality of characters. In mapping the binary data bits into the predetermined character set to produce the plurality of characters, each N bytes of binary data are expanded into M one byte characters where N is an integer, M is an integer and M is larger than N. In a described embodiment, N is equal to three and M is equal to 4.

摘要翻译： 系统包括输入，字符集映射功能和字符集压缩功能。 该输入接收二进制数据，该二进制数据包括可被组织成多个二进制数据字节的多个二进制数据位。 字符集映射功能将二进制数据位映射到预定字符集中以产生多个字符。 字符集压缩功能使用字符集压缩算法压缩多个字符以产生多个压缩字符。 在压缩字符集数据之后，可以经由调制解调器调制多个压缩字符，并通过数据链路传送到接收位置。 在接收位置，解调器接收调制数据并解调调制数据以产生多个压缩字符。 然后，字符集解压缩功能解压缩多个压缩字符以产生多个字符。 然后，二进制数据提取功能从多个字符中提取二进制数据。 在将二进制数据位映射到预定字符集中以产生多个字符时，每个N字节的二进制数据被扩展为M个一字节字符，其中N是整数，M是整数，M大于N.在a N等于3，M等于4。