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公开(公告)号：US20240364493A1
公开(公告)日：2024-10-31
申请号：US18141189
申请日：2023-04-28
申请人： Analog Devices, Inc.
CPC分类号： H04L7/0025 , H04L7/0087 , H04L7/0337
摘要： A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.
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公开(公告)号：US20240348420A1
公开(公告)日：2024-10-17
申请号：US18647834
申请日：2024-04-26
发明人： Jerzy A. Teterwak
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/087 , H04L7/0004
摘要： A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
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公开(公告)号：US12120210B2
公开(公告)日：2024-10-15
申请号：US17993776
申请日：2022-11-23
申请人： Marvell Asia Pte Ltd
发明人： Basel Alnabulsi , Yu Liao , Benjamin Smith , Jamal Riani
CPC分类号： H04L7/0012 , H04L7/033
摘要： An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.
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公开(公告)号：US20240322994A1
公开(公告)日：2024-09-26
申请号：US18481226
申请日：2023-10-04
发明人： Michael Chung WANG , Neal HAYS , Amir AMIRKHANY
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/099
摘要： A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.
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公开(公告)号：US20240322829A1
公开(公告)日：2024-09-26
申请号：US18732176
申请日：2024-06-03
申请人： Ciena Corporation
CPC分类号： H03L7/0814 , H03L7/0994 , H03L7/1976 , H04L7/0037 , H04L7/033
摘要： A transceiver includes a first transmit (Tx) component configured to connect to a second receive (Rx) component in a second transceiver; a first Rx component configured to connect to a second Tx component in the second transceiver; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to continuously calibrate a first Look-Up Table (LUT) configured to feed operating codes to a first phase rotator connected to an output of the single PLL circuit and to one of the first Tx component and the first Rx component. In an embodiment, the control circuit is further configured to continuously calibrate a second LUT configured to feed operating codes to a second phase rotator connected to an output of a single PLL circuit in the second transceiver.
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公开(公告)号：US12101094B2
公开(公告)日：2024-09-24
申请号：US18095472
申请日：2023-01-10
发明人： Daniel Hyman , Jeffrey Norris , Michael Dekoker , Anthony Aquino
CPC分类号： H03L7/099 , H03C3/0908 , H03F3/45475 , H04B1/0007 , H04B1/7136 , H04L7/033
摘要： An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.
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公开(公告)号：US12081231B2
公开(公告)日：2024-09-03
申请号：US18470413
申请日：2023-09-19
发明人： Ching-Hsiang Chang , Yu-Hsun Chien
CPC分类号： H03M1/466 , G05F1/461 , G05F1/468 , H03L7/0807 , H03L7/0891 , H03M1/1245 , H03M1/462 , H04B1/40 , H04L7/0331
摘要： A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.
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公开(公告)号：US12066958B2
公开(公告)日：2024-08-20
申请号：US18135095
申请日：2023-04-14
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
CPC分类号： G06F13/1689 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F13/161 , G06F13/1657 , G11C7/222 , G11C7/04 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
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公开(公告)号：US20240275573A1
公开(公告)日：2024-08-15
申请号：US18644860
申请日：2024-04-24
申请人： SK hynix Inc.
发明人： Dae Sik PARK , Byung Cheol KANG , Seung Duk CHO
CPC分类号： H04L7/005 , H04L7/0079 , H04L7/0091 , H04L7/033
摘要： A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.
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公开(公告)号：US12052045B2
公开(公告)日：2024-07-30
申请号：US17124308
申请日：2020-12-16
发明人： Boris Sijanec
CPC分类号： H04B1/40 , H04L7/0331 , H04L12/2801 , H03L7/08 , H04W88/08
摘要： Provided are systems and methods for transmitting radio signals. A system for transmitting radio signals includes a base station and a customer premises equipment (CPE). The base station includes a first frequency converter and at least one first antenna. The first frequency converter is configured to receive a first radio signal having a predetermined frequency and convert the first radio signal into a second radio signal. The second radio signal has a frequency higher than the predetermined frequency. The at least one first antenna has a transmitter and is configured to wirelessly transmit, via the transmitter, the second radio signal to the CPE. The CPE includes at least one second antenna configured to receive the second radio signal from the at least one first antenna and a second frequency converter configured to convert the second radio signal into the first radio signal.
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