COAXIAL VIA SHIELDED INTERPOSER
    3.
    发明申请

    公开(公告)号:US20230063808A1

    公开(公告)日:2023-03-02

    申请号:US17465596

    申请日:2021-09-02

    申请人: Apple Inc.

    摘要: A coaxial interposer may shield certain signals (e.g., noisy signals, high speed signals, radio frequency (RF) signals) transmitted through an electronic device. The coaxial interposer may include a coaxial via that includes an outer barrel of non-conductive material and an inner barrel of non-conductive material separated by a conductive barrel. Further, the outer barrel of non-conductive material may be enclosed by an outer metal coating. The coaxial via serves to internally shield each signals transmitted between layers of a printed circuit board (PCB) within the electronic device.

    SUBSTRATE WITH BURIED COMPONENT AND MANUFACTURE METHOD THEREOF

    公开(公告)号:US20230058180A1

    公开(公告)日:2023-02-23

    申请号:US17505686

    申请日:2021-10-20

    摘要: A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

    Apparatus and method for impedance balancing of long radio frequency (RF) via

    公开(公告)号:US11564316B2

    公开(公告)日:2023-01-24

    申请号:US17280269

    申请日:2019-11-21

    IPC分类号: H05K1/11 H05K1/02 H05K3/42

    摘要: An apparatus comprising a stack of printed circuit board (PCB) layers having a primary longitudinal structure forming a radio frequency (RE) via including a principal tuning section (223) and a constant longitudinal structure (227) along a conductive column support (255) journaled through the layers in the via. The principal section (221) comprising a first tuning sub-assembly (229 A) in a first portion of the RE via above the longitudinal structure (227) and at an entrance of the primary longitudinal structure (221) and comprising a first set of pad, anti-pad pairs (445, 545, 645) tuned to receive an RE band. A second principal tuning sub-assembly (229B) in a second portion of the via below the longitudinal structure (227) and at an exit of the primary longitudinal structure and comprising a second set of pad, anti-pad pairs (445, 545, 645) tuned to receive the band and mirroring the first set of pairs.

    High-current PCB traces
    7.
    发明授权

    公开(公告)号:US11564309B2

    公开(公告)日:2023-01-24

    申请号:US16704540

    申请日:2019-12-05

    IPC分类号: H05K1/02 H05K3/42

    摘要: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

    Microcontroller board for the learning and practice of coding

    公开(公告)号:US11545051B2

    公开(公告)日:2023-01-03

    申请号:US16295005

    申请日:2019-03-07

    申请人: Hanoi Ju

    发明人: Hanoi Ju

    摘要: Disclosed herein is a microcontroller board for the learning and practice of coding. In the microcontroller board, a platform area (S1) including a platform circuit board (10) in which a microcontroller is provided and module areas (S2) each having a cut line and including a module circuit board (20) are divided and formed on a single board array (S), corresponding header socket holes H are formed in the platform area (S1) including the platform circuit board (10) and the module areas (S2) on both sides of each of the cut lines, a plurality of machine holes (30) is provided along each of the cut lines between the header socket holes (H), via holes (40) are formed by plating the inner circumferential surfaces of the machine holes (30) with metal layers (35) in order to conduct electricity, and V-cut grooves (50) are formed along each of the cut lines.