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公开(公告)号:US20240361794A1
公开(公告)日:2024-10-31
申请号:US18309340
申请日:2023-04-28
摘要: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
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公开(公告)号:US20240345613A1
公开(公告)日:2024-10-17
申请号:US18298875
申请日:2023-04-11
发明人: Paul M. Werking
摘要: Voltage reference circuits configured to output reference voltages with a reduced noise on the output and reduced power consumption when compared to other arrangements of voltage reference circuits. The voltage reference circuit of this disclosure may stack two or more independent shunt voltage reference circuits in series to produce a summed voltage (Vsum), then amplify the summed voltage to output the desired reference voltage. The circuit of this disclosure may arrange the independent shunt voltage reference circuits to diminish any noise generated by each independent shunt voltage reference circuit in the summed voltage, for example as an array of independent shunt voltage reference circuits in series.
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公开(公告)号:US20240345612A1
公开(公告)日:2024-10-17
申请号:US18756323
申请日:2024-06-27
摘要: A voltage reference includes a PMOS transistor including a gate and drain coupled to an input and a source coupled to a voltage node through a resistor, three PMOS transistors including gates coupled to the input and sources coupled to the voltage node through resistors, an n-type flipped-gate transistor including a gate and drain coupled to a PMOS transistor drain and a source coupled to a negative supply node, an NMOS transistor including a gate coupled to the n-type flipped-gate transistor gate, a drain coupled to a PMOS transistor drain, and a source coupled to an output, an NMOS transistor including a gate coupled to a PMOS transistor drain, a drain coupled to the output, and a source coupled to the negative supply node through a resistor, and an NMOS transistor including a drain coupled to the output and a gate and source coupled to the negative supply node.
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公开(公告)号:US20240329674A1
公开(公告)日:2024-10-03
申请号:US18611321
申请日:2024-03-20
摘要: The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit. The voltage reference circuit includes a first enhancement MOSFET transistor, which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground by its source through a source resistor, on which a reference voltage, sum of the PTAT voltage drop on the source resistor and of the gate source voltage of the enhancement MOSFET transistor being formed. The first enhancement MOSFET transistor is arranged on the first branch and coupled by the drain to the first depletion MOSFET transistor in a control node. The control node is coupled to the gate of the first enhancement MOSFET transistor. The first depletion MOSFET transistor injects a PTAT current in the first branch determining a PTAT voltage drop on the source resistor. The second branch includes an output stage coupled between the voltage to regulate and an output node on which the regulated voltage is taken. The output stage includes a second depletion MOSFET transistor on which output is taken at the output node. A resistive voltage divider is coupled to the output node, outputting on a respective divider output node a divided output regulated voltage which is inputted as the process variable of a negative feedback loop which is also coupled to the reference voltage. The output of the negative feedback loop controls the gate of the second MOSFET transistor.
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5.
公开(公告)号:US12079022B2
公开(公告)日:2024-09-03
申请号:US18493796
申请日:2023-10-24
申请人: Apple Inc.
IPC分类号: G05F3/26 , G05F3/20 , G11C5/14 , G11C11/4074
CPC分类号: G05F3/26 , G05F3/205 , G11C5/147 , G11C11/4074
摘要: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.
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公开(公告)号:US20240231403A1
公开(公告)日:2024-07-11
申请号:US18151602
申请日:2023-01-09
发明人: Weibing Jing , Qi Yang , Liang Zhang
CPC分类号: G05F1/575 , G05F1/5735 , G05F3/262 , H02M3/1582
摘要: A power supply circuit includes an amplifier and first and second transistors. The amplifier is configured to provide a drive potential at its output. The first transistor is coupled between a voltage supply terminal and an output terminal, and has a first control terminal coupled to the amplifier output, and is configured to receive at least a portion of the drive potential at the first control terminal. The second transistor is coupled between the first control terminal and the output terminal, and has a second control terminal coupled to the amplifier output. A threshold voltage of the first transistor is lower than a threshold voltage of the second transistor. The second transistor can operate to adaptively reduce the portion of the drive potential at the first control terminal, for example, by the second transistor turning on responsive to a voltage at the output terminal being lower than a voltage level.
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公开(公告)号:US20240201724A1
公开(公告)日:2024-06-20
申请号:US18155490
申请日:2023-01-17
发明人: HIROYUKI KIMURA
摘要: The disclosure: a positive mirror FET, through which a positive mirror current that is proportional to a positive-direction current in currents of an output FET in positive and negative directions is made to flow; a first operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the positive mirror current of the positive mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the positive mirror current of the positive mirror FET by converting an output voltage into a current and feeding back the current to the other end; a negative mirror FET, through which a negative mirror current that is proportional to a negative-direction current in the currents of the output FET in positive and negative directions is made to flow; and a second operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the negative mirror current of the negative mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the negative mirror current of the negative mirror FET by converting an output voltage into a current and feeding back the current to the other end. A detection value is output based on an output current obtained by adding a positive output current corresponding to the output of the first operational amplifier and a negative output current corresponding to the output of the second operational amplifier.
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公开(公告)号:US20240201723A1
公开(公告)日:2024-06-20
申请号:US18082942
申请日:2022-12-16
发明人: Nishant Singh THAKUR
摘要: An apparatus comprising a bias current generator for generating a bias current, the bias current generator comprising two or more negative threshold transistors of the same type and coupled in series.
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9.
公开(公告)号:US12015024B2
公开(公告)日:2024-06-18
申请号:US18060244
申请日:2022-11-30
发明人: Youngjae Kim
CPC分类号: H01L27/0222 , G05F3/205 , G05F3/26 , H01L27/0928 , H02M3/073 , H02M3/078 , H10B12/50
摘要: A body bias voltage generating circuit includes a current mirror circuit configured to generate and input a target current to a target semiconductor element, the target semiconductor element configured to be set to a turned-on state; and a charge pump circuit including an oscillator configured to output a clock signal based on a result of comparing an output voltage of the target semiconductor element with a reference voltage, and at least one charge pump outputting a body bias voltage to each of a plurality of semiconductor elements, wherein each of the plurality of semiconductor elements is the same as or is the same type as the target semiconductor element.
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公开(公告)号:US20240168510A1
公开(公告)日:2024-05-23
申请号:US18423948
申请日:2024-01-26
CPC分类号: G05F3/265 , G05F3/222 , G05F3/225 , G05F3/30 , H03F3/45179
摘要: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.
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