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公开(公告)号：US11636903B2
公开(公告)日：2023-04-25
申请号：US17473269
申请日：2021-09-13
申请人： Kioxia Corporation
发明人： Huy Cu Ngo
摘要： According to the one embodiment, a semiconductor circuit includes: an analog-to-digital conversion circuit including a first analog-to-digital converter configured to sample at least one first sampling signal regarding an input signal based on a first clock, and a second analog-to-digital converter configured to sample at least one second sampling signal regarding the input signal based on a second clock shifted from the first clock by a first time; and a first calibration circuit configured to calibrate at least one timing of the first clock and the second clock based on a calculation result of a moving average of the first sampling signal and the second sampling signal.
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公开(公告)号：US11630788B2
公开(公告)日：2023-04-18
申请号：US16921061
申请日：2020-07-06
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
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公开(公告)号：US20230115615A1
公开(公告)日：2023-04-13
申请号：US17486675
申请日：2021-09-27
IPC分类号： G01R31/3177 , G06F1/10
摘要： Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.
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公开(公告)号：US20230099269A1
公开(公告)日：2023-03-30
申请号：US17565503
申请日：2021-12-30
发明人： Vinod Kumar JAIN , Chi-Yeu CHAO
摘要： A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.
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公开(公告)号：US20230090529A1
公开(公告)日：2023-03-23
申请号：US18071635
申请日：2022-11-30
发明人： Tsung-Che Lu , Chin-Ming Fu , Chih-Hsien Chang
摘要： An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.
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公开(公告)号：US11592860B2
公开(公告)日：2023-02-28
申请号：US17470535
申请日：2021-09-09
发明人： Dohyung Kim , Minyoung Kang
摘要： A system on chip includes: a functional circuit configured to perform a processing operation by receiving a supply voltage; a droop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a droop of the supply voltage has occurred; a clock generation circuit configured to output a first clock signal having a first frequency; and a clock modulation circuit configured to receive the detection signal and the first clock signal, and provide a system clock signal to the functional circuit.
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7.发明申请公开(公告)号：US20230053440A1
公开(公告)日：2023-02-23
申请号：US17820007
申请日：2022-08-16
发明人： Ivo Leonardus COENEN
摘要： In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.
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公开(公告)号：US20230041331A1
公开(公告)日：2023-02-09
申请号：US17975010
申请日：2022-10-27
申请人： SK hynix Inc.
发明人： Gyu Tae PARK
摘要： A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.
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公开(公告)号：US11561572B2
公开(公告)日：2023-01-24
申请号：US17136579
申请日：2020-12-29
发明人： Leon Goldin , Greg Armstrong
摘要： Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.
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公开(公告)号：US11550654B2
公开(公告)日：2023-01-10
申请号：US17100775
申请日：2020-11-20
摘要： Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.
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